1999-08-29 21:06:43 +04:00
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/* $NetBSD: pciide_cy693_reg.h,v 1.3 1999/08/29 17:06:43 bouyer Exp $ */
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1998-11-21 19:06:45 +03:00
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for Contaq/Cypress's CY82693U PCI IDE controller.
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1998-12-03 17:06:16 +03:00
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* Available from http://www.cypress.com/japan/prodgate/chip/cy82c693.html
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1998-11-21 19:06:45 +03:00
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* This chip has 2 PCI IDE functions, each of them has only one channel
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* So there's no primary/secodary distinction in the registers defs.
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*/
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/* IDE control register */
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#define CY_CTRL 0x40
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#define CY_CTRL_RETRY 0x00002000
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#define CY_CTRL_SLAVE_PREFETCH 0x00000400
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#define CY_CTRL_POSTWRITE 0x00000200
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#define CY_CTRL_PREFETCH(drive) (0x00000100 << (2 * (drive)))
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#define CY_CTRL_POSTWRITE_LENGTH_MASK 0x00000030
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#define CY_CTRL_POSTWRITE_LENGTH_OFF 4
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#define CY_CTRL_PREFETCH_LENGTH_MASK 0x00000003
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#define CY_CTRL_PREFETCH_LENGTH_OFF 0
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/* IDE addr setup control register */
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#define CY_ADDR_CTRL 0x48
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#define CY_ADDR_CTRL_SETUP_OFF(drive) (4 * (drive))
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#define CY_ADDR_CTRL_SETUP_MASK(drive) \
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(0x00000007 << CY_ADDR_CTRL_SETUP_OFF(drive))
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/* command control register */
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#define CY_CMD_CTRL 0x4c
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#define CY_CMD_CTRL_IOW_PULSE_OFF(drive) (12 + 16 * (drive))
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#define CY_CMD_CTRL_IOW_REC_OFF(drive) (8 + 16 * (drive))
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#define CY_CMD_CTRL_IOR_PULSE_OFF(drive) (4 + 16 * (drive))
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#define CY_CMD_CTRL_IOR_REC_OFF(drive) (0 + 16 * (drive))
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static int8_t cy_pio_pulse[] = {9, 4, 3, 2, 2};
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static int8_t cy_pio_rec[] = {9, 7, 4, 2, 0};
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#ifdef unused
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static int8_t cy_dma_pulse[] = {7, 2, 2};
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static int8_t cy_dma_rec[] = {7, 1, 0};
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#endif
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1999-08-29 21:06:43 +04:00
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/*
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* The cypress is quite weird: it uses 8-bit ISA registers to control
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* DMA modes.
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*/
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#define CY_DMA_ADDR 0x22
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#define CY_DMA_SIZE 0x2
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#define CY_DMA_IDX 0x00
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#define CY_DMA_IDX_PRIMARY 0x30
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#define CY_DMA_IDX_SECONDARY 0x31
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#define CY_DMA_IDX_TIMEOUT 0x32
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#define CY_DMA_DATA 0x01
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/* Multiword DMA transfer, for CY_DMA_IDX_PRIMARY or CY_DMA_IDX_SECONDARY */
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#define CY_DMA_DATA_MODE_MASK 0x03
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#define CY_DMA_DATA_SINGLE 0x04
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