149 lines
6.4 KiB
C
149 lines
6.4 KiB
C
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/*
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* Copyright (c) 1991-1993 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Computer Systems
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* Engineering Group at Lawrence Berkeley Laboratory.
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* 4. Neither the name of the University nor of the Laboratory may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* From: Header: sbreg.h,v 1.3 93/07/18 14:07:28 mccanne Exp (LBL)
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* $Id: sbreg.h,v 1.1 1994/01/09 19:35:10 cgd Exp $
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*/
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/*
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* SoundBlaster register definitions.
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* See "The Developer Kit for Sound Blaster Series, User's Guide" for more
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* complete information (avialable from Creative Labs, Inc.). We refer
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* to this documentation as "SBK".
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*
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* We handle two types of cards: the basic SB version 2.0+, and
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* the SB PRO. There are several distinct pieces of the hardware:
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*
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* joystick port (independent of I/O base address)
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* FM synth (stereo on PRO)
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* mixer (PRO only)
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* DSP (sic)
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* CD-ROM (PRO only)
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*
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* The MIDI capabilities are handled by the DSP unit.
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*/
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/*
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* Address map. The SoundBlaster can be configured (via jumpers) for
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* either base I/O address 0x220 or 0x240. The encodings below give
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* the offsets to specific SB ports. SBP stands for SB port offset.
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*/
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#ifdef SBPRO
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#define SBP_LFM_STATUS 0 /* R left FM status port */
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#define SBP_LFM_ADDR 0 /* W left FM address register */
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#define SBP_LFM_DATA 1 /* RW left FM data port */
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#define SBP_RFM_STATUS 2 /* R right FM status port */
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#define SBP_RFM_ADDR 2 /* W right FM address register */
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#define SBP_RFM_DATA 3 /* RW right FM data port */
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#endif
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#define SBP_FM_STATUS 8 /* R FM status port */
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#define SBP_FM_ADDR 8 /* W FM address register */
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#define SBP_FM_DATA 9 /* RW FM data port */
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#ifdef SBPRO
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#define SBP_MIXER_ADDR 4 /* W mixer address register */
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#define SBP_MIXER_DATA 5 /* RW mixer data port */
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#endif
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#define SBP_DSP_RESET 6 /* W reset port */
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#define SB_MAGIC 0xaa /* card outputs on successful reset */
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#define SBP_DSP_READ 10 /* R read port */
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#define SBP_DSP_WRITE 12 /* W write port */
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#define SBP_DSP_WSTAT 12 /* R write status */
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#define SBP_DSP_RSTAT 14 /* R read status */
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#define SB_DSP_BUSY 0x80
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#define SB_DSP_READY 0x80
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#ifdef SBPRO
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#define SBP_CDROM_DATA 16 /* RW send cmds/recv data */
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#define SBP_CDROM_STATUS 17 /* R status port */
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#define SBP_CDROM_RESET 18 /* W reset register */
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#define SBP_CDROM_ENABLE 19 /* W enable register */
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#endif
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#ifdef SBPRO
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#define SB_NPORT 24
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#else
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#define SB_NPORT 16
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#endif
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/*
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* DSP commands. This unit handles MIDI and audio capabilities.
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* The DSP can be reset, data/commands can be read or written to it,
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* and it can generate interrupts. Interrupts are generated for MIDI
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* input or DMA completion. They seem to have neglected the fact
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* that it would be nice to have a MIDI transmission complete interrupt.
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* Worse, the DMA engine is half-duplex. This means you need to do
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* (timed) programmed I/O to be able to record and play simulataneously.
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*/
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#define SB_DSP_DACWRITE 0x10 /* programmed I/O write to DAC */
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#define SB_DSP_WDMA 0x14 /* begin 8-bit linear DMA output */
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#define SB_DSP_WDMA_2 0x16 /* begin 2-bit ADPCM DMA output */
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#define SB_DSP_ADCREAD 0x20 /* programmed I/O read from ADC */
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#define SB_DSP_RDMA 0x24 /* begin 8-bit linear DMA input */
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#define SB_MIDI_POLL 0x30 /* initiate a polling read for MIDI */
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#define SB_MIDI_READ 0x31 /* read a MIDI byte on recv intr */
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#define SB_MIDI_UART_POLL 0x34 /* enter UART mode w/ read polling */
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#define SB_MIDI_UART_INTR 0x35 /* enter UART mode w/ read intrs */
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#define SB_MIDI_WRITE 0x38 /* write a MIDI byte (non-UART mode) */
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#define SB_DSP_TIMECONST 0x40 /* set ADAC time constant */
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#define SB_DSP_BLOCKSIZE 0x48 /* set blk size for high speed xfer */
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#define SB_DSP_WDMA_4 0x74 /* begin 4-bit ADPCM DMA output */
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#define SB_DSP_WDMA_2_6 0x76 /* begin 2.6-bit ADPCM DMA output */
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#define SB_DSP_SILENCE 0x80 /* send a block of silence */
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#define SB_DSP_HS_OUTPUT 0x91 /* set high speed mode for wdma */
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#define SB_DSP_HS_INPUT 0x99 /* set high speed mode for rdma */
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#define SB_DSP_HALT 0xd0 /* temporarilty suspend DMA */
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#define SB_DSP_SPKR_ON 0xd1 /* turn speaker on */
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#define SB_DSP_SPKR_OFF 0xd3 /* turn speaker off */
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#define SB_DSP_CONT 0xd4 /* continue suspended DMA */
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#define SB_DSP_RD_SPKR 0xd8 /* get speaker status */
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#define SB_SPKR_OFF 0x00
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#define SB_SPKR_ON 0xff
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#define SB_DSP_VERSION 0xe1 /* get version number */
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/*
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* The ADPCM encodings are differential, meaning each sample represents
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* a difference to add to a running sum. The inital value is called the
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* reference, or reference byte. Any of the ADPCM DMA transfers can specify
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* that the given transfer begins with a reference byte by or'ing
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* in the bit below.
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*/
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#define SB_DSP_REFERENCE 1
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/*
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* Macros to detect valid hardware configuration data.
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*/
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#define SB_IRQ_VALID(mask) ((mask) & 0x00ac) /* IRQ 2,3,5,7 */
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#define SB_DRQ_VALID(chan) ((chan) == 1)
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#define SB_BASE_VALID(chan) ((base) == 0x220 || (base) == 0x240)
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#define SB_INPUT_RATE 0
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#define SB_OUTPUT_RATE 1
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