99 lines
4.7 KiB
C
99 lines
4.7 KiB
C
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/* $NetBSD: trap.h,v 1.1 1999/09/13 10:31:23 itojun Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)trap.h 5.4 (Berkeley) 5/9/91
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*/
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/*
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* Trap type values
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* also known in trap.c for name strings
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*/
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/*
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* SH3 version
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*
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* T.Horiuchi Brains Corp. 05/22/1998
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*/
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#define T_POWERON 0x000 /* Power on */
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#define T_RESET 0x020 /* Reset */
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#define T_TLBMISSR 0x040 /* TLB miss(Read) */
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#define T_TLBINVALIDR 0x040 /* Invalid TLB(Read) */
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#define T_TLBMISSW 0x060 /* TLB miss(Write) */
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#define T_TLBINVALIDW 0x060 /* Invalid TLB(Write) */
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#define T_INITPAGEWR 0x080 /* Initial Page write */
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#define T_TLBPRIVR 0x0a0 /* TLB privilege violation(Read) */
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#define T_TLBPRIVW 0x0c0 /* TLB privilege violation(Write) */
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#define T_ADDRESSERRR 0x0e0 /* Address Error(Read) */
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#define T_ADDRESSERRW 0x100 /* Address Error(Write) */
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#define T_TRAP 0x160 /* trapa instruction */
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#define T_INVALIDISN 0x180 /* Invalid instruction */
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#define T_INVALIDSLOT 0x1a0 /* Invalid slot instruction */
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#define T_USERBREAK 0x1e0 /* User break */
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#define T_NMI 0x1c0 /* NMI */
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#define T_EXTINT0 0x200 /* External Interrupt IRL=0 */
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#define T_EXTINT1 0x220 /* External Interrupt IRL=1 */
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#define T_EXTINT2 0x240 /* External Interrupt IRL=2 */
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#define T_EXTINT3 0x260 /* External Interrupt IRL=3 */
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#define T_EXTINT4 0x280 /* External Interrupt IRL=4 */
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#define T_EXTINT5 0x2a0 /* External Interrupt IRL=5 */
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#define T_EXTINT6 0x2c0 /* External Interrupt IRL=6 */
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#define T_EXTINT7 0x2e0 /* External Interrupt IRL=7 */
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#define T_EXTINT8 0x300 /* External Interrupt IRL=8 */
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#define T_EXTINT9 0x320 /* External Interrupt IRL=9 */
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#define T_EXTINT10 0x340 /* External Interrupt IRL=10 */
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#define T_EXTINT11 0x360 /* External Interrupt IRL=11 */
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#define T_EXTINT12 0x380 /* External Interrupt IRL=12 */
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#define T_EXTINT13 0x3a0 /* External Interrupt IRL=13 */
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#define T_EXTINT14 0x3c0 /* External Interrupt IRL=14 */
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#define T_PIN_TMU0 0x400 /* Peripheral Interrupt(TMU0) */
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#define T_PIN_TMU1 0x420 /* Peripheral Interrupt(TMU1) */
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#define T_PIN_TMU2_TUNI2 0x440 /* Peripheral Interrupt(TMU2_TUNI2) */
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#define T_PIN_TMU2_TICPI2 0x460 /* Peripheral Interrupt(TMU2_TICPI2) */
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#define T_PIN_RTC_ATI 0x480 /* Peripheral Interrupt(RTC_ATI) */
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#define T_PIN_RTC_PRI 0x4a0 /* Peripheral Interrupt(RTC_PRI) */
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#define T_PIN_RTC_CUI 0x4c0 /* Peripheral Interrupt(RTC_CUI) */
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#define T_PIN_SCI_ERI 0x4e0 /* Peripheral Interrupt(SCI_ERI) */
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#define T_PIN_SCI_RXI 0x500 /* Peripheral Interrupt(SCI_RXI) */
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#define T_PIN_SCI_TXI 0x520 /* Peripheral Interrupt(SCI_TXI) */
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#define T_PIN_SCI_TEI 0x540 /* Peripheral Interrupt(SCI_TEI) */
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#define T_PIN_WDT 0x560 /* Peripheral Interrupt(WDT) */
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#define T_PIN_REF_RCMI 0x580 /* Peripheral Interrupt(REF_RCMI) */
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#define T_PIN_REF_ROVI 0x5a0 /* Peripheral Interrupt(REF_ROVI) */
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#define T_ASTFLT 0xf00 /* Asynchronous system trap */
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#define T_USER 0x001 /* Trap in user mode */
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