1996-12-05 10:01:30 +03:00
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/* $NetBSD: ad1848.c,v 1.14 1996/12/05 07:01:30 mikel Exp $ */
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1995-02-21 05:26:39 +03:00
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/*
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* Copyright (c) 1994 John Brezak
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* Copyright (c) 1991-1993 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Computer Systems
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* Engineering Group at Lawrence Berkeley Laboratory.
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* 4. Neither the name of the University nor of the Laboratory may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Copyright by Hannu Savolainen 1994
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer. 2.
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Portions of this code are from the VOXware support for the ad1848
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* by Hannu Savolainen <hannu@voxware.pp.fi>
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*
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* Portions also supplied from the SoundBlaster driver for NetBSD.
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*/
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/*
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* Todo:
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* - Need datasheet for CS4231 (for use with GUS MAX)
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* - Use fast audio_dma
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/proc.h>
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#include <sys/buf.h>
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#include <machine/cpu.h>
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#include <machine/pio.h>
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#include <sys/audioio.h>
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#include <dev/audio_if.h>
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1995-04-17 16:06:30 +04:00
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmavar.h>
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1995-02-21 05:26:39 +03:00
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1995-07-07 06:11:45 +04:00
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#include <dev/ic/ad1848reg.h>
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#include <dev/ic/cs4231reg.h>
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1995-04-17 19:48:20 +04:00
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#include <dev/isa/ad1848var.h>
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1995-07-07 06:11:45 +04:00
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#include <dev/isa/cs4231var.h>
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1995-02-21 05:26:39 +03:00
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1995-07-07 06:11:45 +04:00
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#ifdef AUDIO_DEBUG
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1995-02-21 05:26:39 +03:00
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extern void Dprintf __P((const char *, ...));
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#define DPRINTF(x) if (ad1848debug) Dprintf x
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int ad1848debug = 0;
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#else
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#define DPRINTF(x)
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#endif
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/*
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* Initial values for the indirect registers of CS4248/AD1848.
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*/
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static int ad1848_init_values[] = {
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1996-12-05 10:01:30 +03:00
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/* Left Input Control */
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1995-02-21 05:26:39 +03:00
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GAIN_12|INPUT_MIC_GAIN_ENABLE,
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1996-12-05 10:01:30 +03:00
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/* Right Input Control */
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1995-02-21 05:26:39 +03:00
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GAIN_12|INPUT_MIC_GAIN_ENABLE,
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ATTEN_12, /* Left Aux #1 Input Control */
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ATTEN_12, /* Right Aux #1 Input Control */
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ATTEN_12, /* Left Aux #2 Input Control */
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ATTEN_12, /* Right Aux #2 Input Control */
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1995-07-07 06:11:45 +04:00
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/* bits 5-0 are attenuation select */
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1996-12-05 10:01:30 +03:00
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ATTEN_12, /* Left DAC output Control */
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ATTEN_12, /* Right DAC output Control */
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/* Clock and Data Format */
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CLOCK_XTAL1|FMT_PCM8,
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/* Interface Config */
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SINGLE_DMA|AUTO_CAL_ENABLE,
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1995-02-21 05:26:39 +03:00
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INTERRUPT_ENABLE, /* Pin control */
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0x00, /* Test and Init */
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0xca, /* Misc control */
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ATTEN_0<<2, /* Digital Mix Control */
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0, /* Upper base Count */
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1995-07-07 06:11:45 +04:00
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0, /* Lower base Count */
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1996-12-05 10:01:30 +03:00
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/* These are for CS4231 &c. only (additional registers): */
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1995-07-07 06:11:45 +04:00
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0, /* Alt feature 1 */
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0, /* Alt feature 2 */
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ATTEN_12, /* Left line in */
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ATTEN_12, /* Right line in */
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0, /* Timer low */
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0, /* Timer high */
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0, /* unused */
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0, /* unused */
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0, /* IRQ status */
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0, /* unused */
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1996-12-05 10:01:30 +03:00
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/* Mono input (mic) Control */
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1995-07-07 06:11:45 +04:00
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MONO_INPUT_MUTE|ATTEN_6, /* mute mic by default */
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0, /* unused */
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0, /* record format */
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0, /* upper record count */
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1996-12-05 10:01:30 +03:00
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0 /* lower record count */
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1995-02-21 05:26:39 +03:00
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};
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void ad1848_reset __P((struct ad1848_softc *));
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int ad1848_set_speed __P((struct ad1848_softc *, int));
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1996-04-30 00:02:32 +04:00
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int ad1848_set_format __P((struct ad1848_softc *, int, int));
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void ad1848_mute_monitor __P((void *, int));
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static int ad_read __P((struct ad1848_softc *, int));
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static __inline void ad_write __P((struct ad1848_softc *, int, int));
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static void ad_set_MCE __P((struct ad1848_softc *, int));
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static void wait_for_calibration __P((struct ad1848_softc *));
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1995-02-21 05:26:39 +03:00
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static int
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ad_read(sc, reg)
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struct ad1848_softc *sc;
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int reg;
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{
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int x;
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outb(sc->sc_iobase+AD1848_IADDR, (u_char) (reg & 0xff) | sc->MCE_bit);
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x = inb(sc->sc_iobase+AD1848_IDATA);
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1996-10-13 05:37:04 +04:00
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/* printf("(%02x<-%02x) ", reg|sc->MCE_bit, x); */
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1995-02-21 05:26:39 +03:00
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return x;
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}
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1996-04-30 00:02:32 +04:00
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static __inline void
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1995-02-21 05:26:39 +03:00
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ad_write(sc, reg, data)
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struct ad1848_softc *sc;
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int reg;
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int data;
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{
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outb(sc->sc_iobase+AD1848_IADDR, (u_char) (reg & 0xff) | sc->MCE_bit);
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outb(sc->sc_iobase+AD1848_IDATA, (u_char) (data & 0xff));
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1996-10-13 05:37:04 +04:00
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/* printf("(%02x->%02x) ", reg|sc->MCE_bit, data); */
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1995-02-21 05:26:39 +03:00
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}
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static void
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ad_set_MCE(sc, state)
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struct ad1848_softc *sc;
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int state;
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{
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if (state)
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sc->MCE_bit = MODE_CHANGE_ENABLE;
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else
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sc->MCE_bit = 0;
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outb(sc->sc_iobase+AD1848_IADDR, sc->MCE_bit);
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}
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static void
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wait_for_calibration(sc)
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struct ad1848_softc *sc;
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{
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int timeout = 100000;
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1995-07-07 06:11:45 +04:00
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DPRINTF(("ad1848: Auto calibration started.\n"));
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1995-02-21 05:26:39 +03:00
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/*
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* Wait until the auto calibration process has finished.
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*
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* 1) Wait until the chip becomes ready (reads don't return 0x80).
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* 2) Wait until the ACI bit of I11 gets on and then off.
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*/
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while (timeout > 0 && inb(sc->sc_iobase+AD1848_IADDR) == SP_IN_INIT)
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timeout--;
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if (inb(sc->sc_iobase+AD1848_IADDR) == SP_IN_INIT)
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DPRINTF(("ad1848: Auto calibration timed out(1).\n"));
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1995-07-07 06:11:45 +04:00
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outb(sc->sc_iobase+AD1848_IADDR, SP_TEST_AND_INIT);
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timeout = 100000;
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while (timeout > 0 && inb(sc->sc_iobase+AD1848_IADDR) != SP_TEST_AND_INIT)
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timeout--;
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if (inb(sc->sc_iobase+AD1848_IADDR) == SP_TEST_AND_INIT)
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DPRINTF(("ad1848: Auto calibration timed out(1.5).\n"));
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1995-02-21 05:26:39 +03:00
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if (!(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)) {
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timeout = 100000;
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while (timeout > 0 && !(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG))
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timeout--;
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if (!(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG))
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DPRINTF(("ad1848: Auto calibration timed out(2).\n"));
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}
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timeout = 100000;
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while (timeout > 0 && ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)
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timeout--;
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if (ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)
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DPRINTF(("ad1848: Auto calibration timed out(3).\n"));
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}
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1995-07-07 06:11:45 +04:00
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#ifdef AUDIO_DEBUG
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1996-10-16 05:12:18 +04:00
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void ad1848_dump_regs __P((struct ad1848_softc *));
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1995-02-21 05:26:39 +03:00
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void
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ad1848_dump_regs(sc)
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struct ad1848_softc *sc;
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{
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int i;
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u_char r;
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1996-12-05 10:01:30 +03:00
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printf("ad1848 status=%02x", inb(sc->sc_iobase+AD1848_STATUS));
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1996-10-13 05:37:04 +04:00
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printf(" regs: ");
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1995-02-21 05:26:39 +03:00
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for (i = 0; i < 16; i++) {
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r = ad_read(sc, i);
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1996-12-05 10:01:30 +03:00
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printf("%02x ", r);
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1995-02-21 05:26:39 +03:00
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}
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1996-12-05 10:01:30 +03:00
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if (sc->mode == 2) {
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1995-07-07 06:11:45 +04:00
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for (i = 16; i < 32; i++) {
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r = ad_read(sc, i);
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1996-12-05 10:01:30 +03:00
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printf("%02x ", r);
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1995-07-07 06:11:45 +04:00
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}
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1996-12-05 10:01:30 +03:00
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printf("\n");
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}
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1995-02-21 05:26:39 +03:00
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}
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#endif
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#ifdef NEWCONFIG
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void
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ad1848_forceintr(sc)
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struct ad1848_softc *sc;
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{
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static char dmabuf;
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/*
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* Set up a DMA read of one byte.
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* XXX Note that at this point we haven't called
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* at_setup_dmachan(). This is okay because it just
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* allocates a buffer in case it needs to make a copy,
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* and it won't need to make a copy for a 1 byte buffer.
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* (I think that calling at_setup_dmachan() should be optional;
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* if you don't call it, it will be called the first time
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* it is needed (and you pay the latency). Also, you might
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* never need the buffer anyway.)
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*/
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1996-03-01 07:08:13 +03:00
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isa_dmastart(DMAMODE_READ, &dmabuf, 1, sc->sc_drq);
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1995-02-21 05:26:39 +03:00
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ad_write(sc, SP_LOWER_BASE_COUNT, 0);
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ad_write(sc, SP_UPPER_BASE_COUNT, 0);
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ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE);
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}
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#endif
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/*
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* Probe for the ad1848 chip
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*/
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int
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ad1848_probe(sc)
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struct ad1848_softc *sc;
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{
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1995-11-10 07:30:36 +03:00
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register int iobase = sc->sc_iobase;
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1995-02-21 05:26:39 +03:00
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u_char tmp, tmp1 = 0xff, tmp2 = 0xff;
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int i;
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if (!AD1848_BASE_VALID(iobase)) {
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1996-12-05 10:01:30 +03:00
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#ifdef AUDIO_DEBUG
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printf("ad1848: configured iobase %04x invalid\n", iobase);
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#endif
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1995-02-21 05:26:39 +03:00
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return 0;
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}
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sc->sc_iobase = iobase;
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/* Is there an ad1848 chip ? */
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sc->MCE_bit = MODE_CHANGE_ENABLE;
|
1995-07-07 06:11:45 +04:00
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sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check that the I/O address is in use.
|
|
|
|
*
|
1995-07-07 06:11:45 +04:00
|
|
|
* The SP_IN_INIT bit of the base I/O port is known to be 0 after the
|
|
|
|
* chip has performed its power-on initialization. Just assume
|
1995-02-21 05:26:39 +03:00
|
|
|
* this has happened before the OS is starting.
|
|
|
|
*
|
1995-07-07 06:11:45 +04:00
|
|
|
* If the I/O address is unused, inb() typically returns 0xff.
|
1995-02-21 05:26:39 +03:00
|
|
|
*/
|
1995-07-07 06:11:45 +04:00
|
|
|
if (((tmp = inb(iobase+AD1848_IADDR)) & SP_IN_INIT) != 0x00) { /* Not a AD1848 */
|
|
|
|
DPRINTF(("ad_detect_A %x\n", tmp));
|
1995-02-21 05:26:39 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Test if it's possible to change contents of the indirect registers.
|
|
|
|
* Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
|
|
|
|
* so try to avoid using it.
|
|
|
|
*/
|
|
|
|
ad_write(sc, 0, 0xaa);
|
|
|
|
ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */
|
|
|
|
|
|
|
|
if ((tmp1 = ad_read(sc, 0)) != 0xaa ||
|
|
|
|
(tmp2 = ad_read(sc, 1)) != 0x45) {
|
|
|
|
DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ad_write(sc, 0, 0x45);
|
|
|
|
ad_write(sc, 1, 0xaa);
|
|
|
|
|
|
|
|
if ((tmp1 = ad_read(sc, 0)) != 0x45 ||
|
|
|
|
(tmp2 = ad_read(sc, 1)) != 0xaa) {
|
|
|
|
DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The indirect register I12 has some read only bits. Lets
|
|
|
|
* try to change them.
|
|
|
|
*/
|
|
|
|
tmp = ad_read(sc, SP_MISC_INFO);
|
|
|
|
ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f);
|
|
|
|
|
|
|
|
if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) {
|
|
|
|
DPRINTF(("ad_detect_D (%x)\n", tmp1));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
1995-07-07 06:11:45 +04:00
|
|
|
* MSB and 4 LSBs of the reg I12 tell the chip revision.
|
|
|
|
*
|
|
|
|
* A preliminary version of the AD1846 data sheet stated that it
|
|
|
|
* used an ID field of 0x0B. The current version, however,
|
|
|
|
* states that the AD1846 uses ID 0x0A, just like the AD1848K.
|
|
|
|
*
|
|
|
|
* this switch statement will need updating as newer clones arrive....
|
1995-02-21 05:26:39 +03:00
|
|
|
*/
|
1995-07-07 06:11:45 +04:00
|
|
|
switch (tmp1 & 0x8f) {
|
|
|
|
case 0x09:
|
|
|
|
sc->chip_name = "AD1848J";
|
|
|
|
break;
|
|
|
|
case 0x0A:
|
|
|
|
sc->chip_name = "AD1848K";
|
|
|
|
break;
|
|
|
|
#if 0 /* See above */
|
|
|
|
case 0x0B:
|
|
|
|
sc->chip_name = "AD1846";
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
case 0x81:
|
|
|
|
sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */
|
|
|
|
break;
|
|
|
|
case 0x89:
|
|
|
|
sc->chip_name = "CS4248";
|
|
|
|
break;
|
|
|
|
case 0x8A:
|
|
|
|
sc->chip_name = "broken"; /* CS4231/AD1845; see below */
|
1995-02-21 05:26:39 +03:00
|
|
|
break;
|
1995-07-07 06:11:45 +04:00
|
|
|
default:
|
|
|
|
sc->chip_name = "unknown";
|
|
|
|
DPRINTF(("ad1848: unknown codec version %#02X\n", (tmp1 & 0x8f)));
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
1995-07-07 06:11:45 +04:00
|
|
|
* The original AD1848/CS4248 has just 16 indirect registers. This means
|
1995-02-21 05:26:39 +03:00
|
|
|
* that I0 and I16 should return the same value (etc.).
|
|
|
|
* Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
|
1995-07-07 06:11:45 +04:00
|
|
|
* with CS4231, AD1845, etc.
|
1995-02-21 05:26:39 +03:00
|
|
|
*/
|
|
|
|
ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) {
|
|
|
|
DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
1995-07-07 06:11:45 +04:00
|
|
|
* Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit
|
|
|
|
* The bit 0x80 is always 1 in CS4248, CS4231, and AD1845.
|
1995-02-21 05:26:39 +03:00
|
|
|
*/
|
1995-07-07 06:11:45 +04:00
|
|
|
ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
tmp1 = ad_read(sc, SP_MISC_INFO);
|
1995-07-07 06:11:45 +04:00
|
|
|
if ((tmp1 & 0xc0) == (0x80 | MODE2)) {
|
1995-02-21 05:26:39 +03:00
|
|
|
/*
|
1995-07-07 06:11:45 +04:00
|
|
|
* CS4231 or AD1845 detected - is it?
|
1995-02-21 05:26:39 +03:00
|
|
|
*
|
1995-07-07 06:11:45 +04:00
|
|
|
* Verify that setting I2 doesn't change I18.
|
1995-02-21 05:26:39 +03:00
|
|
|
*/
|
1995-07-07 06:11:45 +04:00
|
|
|
ad_write(sc, 18, 0x88); /* Set I18 to known value */
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
ad_write(sc, 2, 0x45);
|
|
|
|
if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */
|
|
|
|
ad_write(sc, 2, 0xaa);
|
|
|
|
if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */
|
|
|
|
DPRINTF(("ad_detect_H(%x)\n", tmp2));
|
1995-02-21 05:26:39 +03:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
1995-07-07 06:11:45 +04:00
|
|
|
* It's a CS4231, or another clone with 32 registers.
|
|
|
|
* Let's find out which by checking I25.
|
1995-02-21 05:26:39 +03:00
|
|
|
*/
|
1995-07-07 06:11:45 +04:00
|
|
|
if ((tmp1 & 0x8f) == 0x8a) {
|
|
|
|
tmp1 = ad_read(sc, CS_VERSION_ID);
|
|
|
|
switch (tmp1 & 0xe7) {
|
|
|
|
case 0xA0:
|
|
|
|
sc->chip_name = "CS4231A";
|
|
|
|
break;
|
|
|
|
case 0x80:
|
|
|
|
/* XXX I25 no good, AD1845 same as CS4231 */
|
|
|
|
sc->chip_name = "CS4231 or AD1845";
|
|
|
|
break;
|
|
|
|
case 0x82:
|
|
|
|
sc->chip_name = "CS4232";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
sc->mode = 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Wait for 1848 to init */
|
|
|
|
while(inb(sc->sc_iobase+AD1848_IADDR) & SP_IN_INIT);
|
|
|
|
|
|
|
|
/* Wait for 1848 to autocal */
|
|
|
|
outb(sc->sc_iobase+AD1848_IADDR, SP_TEST_AND_INIT);
|
|
|
|
while(inb(sc->sc_iobase+AD1848_IDATA) & AUTO_CAL_IN_PROG);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Attach hardware to driver, attach hardware driver to audio
|
|
|
|
* pseudo-device driver .
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
ad1848_attach(sc)
|
|
|
|
struct ad1848_softc *sc;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct ad1848_volume vol_mid = {150, 150};
|
|
|
|
struct ad1848_volume vol_0 = {0, 0};
|
|
|
|
|
|
|
|
sc->sc_locked = 0;
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
/* Initialize the ad1848... */
|
1995-02-21 05:26:39 +03:00
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
ad_write(sc, i, ad1848_init_values[i]);
|
1995-07-07 06:11:45 +04:00
|
|
|
/* ...and additional CS4231 stuff too */
|
|
|
|
if (sc->mode == 2) {
|
|
|
|
#if 0
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, 0); /* disable SINGLE_DMA feature */
|
|
|
|
#else
|
|
|
|
/* XXX SINGLE_DMA is cleared in ad1848_reset(), due to #if 0 */
|
1995-02-21 05:26:39 +03:00
|
|
|
#endif
|
1995-07-07 06:11:45 +04:00
|
|
|
for (i = 0x10; i <= 0x1F; i++)
|
|
|
|
if (ad1848_init_values[i] != 0)
|
|
|
|
ad_write(sc, i, ad1848_init_values[i]);
|
|
|
|
}
|
|
|
|
ad1848_reset(sc);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
/* Set default encoding (ULAW) */
|
|
|
|
sc->sc_irate = sc->sc_orate = 8000;
|
|
|
|
sc->precision = 8;
|
|
|
|
sc->channels = 1;
|
|
|
|
sc->encoding = AUDIO_ENCODING_ULAW;
|
1995-03-25 03:00:53 +03:00
|
|
|
(void) ad1848_set_in_sr(sc, sc->sc_irate);
|
|
|
|
(void) ad1848_set_out_sr(sc, sc->sc_orate);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
/* Set default gains */
|
|
|
|
(void) ad1848_set_rec_gain(sc, &vol_mid);
|
|
|
|
(void) ad1848_set_out_gain(sc, &vol_mid);
|
|
|
|
(void) ad1848_set_mon_gain(sc, &vol_0);
|
|
|
|
(void) ad1848_set_aux1_gain(sc, &vol_mid); /* CD volume */
|
1995-07-07 06:11:45 +04:00
|
|
|
if (sc->mode == 2) {
|
|
|
|
/* aux1 was really the DAC output */
|
|
|
|
(void) ad1848_set_aux2_gain(sc, &vol_mid); /* CD volume */
|
|
|
|
(void) cs4231_set_linein_gain(sc, &vol_mid);
|
|
|
|
(void) cs4231_set_mono_gain(sc, &vol_0); /* mic */
|
|
|
|
} else
|
|
|
|
(void) ad1848_set_aux2_gain(sc, &vol_0);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
/* Set default port */
|
|
|
|
(void) ad1848_set_rec_port(sc, MIC_IN_PORT);
|
|
|
|
|
1996-10-13 05:37:04 +04:00
|
|
|
printf(": %s", sc->chip_name);
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Various routines to interface to higher level audio driver
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
ad1848_set_rec_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
register u_char reg, gain;
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
DPRINTF(("ad1848_set_rec_gain: %d:%d\n", gp->left, gp->right));
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
sc->rec_gain = *gp;
|
|
|
|
|
|
|
|
gain = (gp->left * GAIN_22_5)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
|
|
|
|
reg &= INPUT_GAIN_MASK;
|
|
|
|
ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain&0x0f)|reg);
|
|
|
|
|
|
|
|
gain = (gp->right * GAIN_22_5)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);
|
|
|
|
reg &= INPUT_GAIN_MASK;
|
|
|
|
ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain&0x0f)|reg);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_rec_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->rec_gain;
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_out_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
u_int atten;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_out_gain: %d:%d\n", gp->left, gp->right));
|
|
|
|
|
|
|
|
sc->out_gain = *gp;
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->left) * OUTPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_LEFT_OUTPUT_CONTROL);
|
1995-07-07 06:11:45 +04:00
|
|
|
reg &= OUTPUT_ATTEN_MASK;
|
1995-02-21 05:26:39 +03:00
|
|
|
ad_write(sc, SP_LEFT_OUTPUT_CONTROL, (atten&0x3f)|reg);
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->right) * OUTPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_RIGHT_OUTPUT_CONTROL);
|
1995-07-07 06:11:45 +04:00
|
|
|
reg &= OUTPUT_ATTEN_MASK;
|
1995-02-21 05:26:39 +03:00
|
|
|
ad_write(sc, SP_RIGHT_OUTPUT_CONTROL, (atten&0x3f)|reg);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_out_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->out_gain;
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
1995-07-07 06:11:45 +04:00
|
|
|
ad1848_set_mon_gain(sc, gp) /* monitor gain */
|
1995-02-21 05:26:39 +03:00
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
u_int atten;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_mon_gain: %d\n", gp->left));
|
|
|
|
|
|
|
|
sc->mon_gain = *gp;
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->left) * OUTPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_DIGITAL_MIX);
|
1995-07-07 06:11:45 +04:00
|
|
|
reg &= MIX_ATTEN_MASK;
|
1995-02-21 05:26:39 +03:00
|
|
|
ad_write(sc, SP_DIGITAL_MIX, (atten&OUTPUT_ATTEN_BITS)|reg);
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_mon_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->mon_gain;
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
int
|
|
|
|
cs4231_set_mono_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-07-07 06:11:45 +04:00
|
|
|
u_char reg, oreg;
|
|
|
|
u_int atten;
|
|
|
|
|
|
|
|
DPRINTF(("cs4231_set_mono_gain: %d\n", gp->left));
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
sc->mono_gain = *gp;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->left) * MONO_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
oreg = reg = ad_read(sc, CS_MONO_IO_CONTROL);
|
|
|
|
reg &= MONO_INPUT_ATTEN_MASK;
|
|
|
|
ad_write(sc, CS_MONO_IO_CONTROL, (atten&MONO_INPUT_ATTEN_BITS)|reg);
|
|
|
|
DPRINTF(("cs4231_set_mono_gain: was:%x\n", oreg));
|
|
|
|
return(0);
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
int
|
|
|
|
cs4231_get_mono_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->mono_gain;
|
|
|
|
return(0);
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
int
|
|
|
|
ad1848_set_mic_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
|
|
|
|
DPRINTF(("cs4231_set_mic_gain: %d\n", gp->left));
|
|
|
|
|
|
|
|
if (gp->left > AUDIO_MAX_GAIN/2) {
|
|
|
|
sc->mic_gain_on = 1;
|
|
|
|
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_INPUT_CONTROL, reg | INPUT_MIC_GAIN_ENABLE);
|
|
|
|
} else {
|
|
|
|
sc->mic_gain_on = 0;
|
|
|
|
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_INPUT_CONTROL, reg & ~INPUT_MIC_GAIN_ENABLE);
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
return(0);
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
int
|
|
|
|
ad1848_get_mic_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
if (sc->mic_gain_on)
|
|
|
|
gp->left = gp->right = AUDIO_MAX_GAIN;
|
|
|
|
else
|
|
|
|
gp->left = gp->right = AUDIO_MIN_GAIN;
|
|
|
|
return(0);
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
void
|
|
|
|
ad1848_mute_monitor(addr, mute)
|
|
|
|
void *addr;
|
|
|
|
int mute;
|
|
|
|
{
|
|
|
|
register struct ad1848_softc *sc = addr;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_mute_monitor: %smuting\n", mute ? "" : "un"));
|
|
|
|
if (sc->mode == 2) {
|
|
|
|
cs4231_mute_monitor(sc, mute);
|
|
|
|
cs4231_mute_mono(sc, mute);
|
|
|
|
cs4231_mute_line(sc, mute);
|
|
|
|
}
|
|
|
|
|
|
|
|
ad1848_mute_aux1(sc, mute);
|
|
|
|
ad1848_mute_aux2(sc, mute);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
cs4231_mute_monitor(sc, mute)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int mute;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
if (mute) {
|
|
|
|
DPRINTF(("cs4231_mute_monitor: muting\n"));
|
|
|
|
reg = ad_read(sc, SP_LEFT_OUTPUT_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_OUTPUT_CONTROL, OUTPUT_MUTE|reg);
|
|
|
|
reg = ad_read(sc, SP_RIGHT_OUTPUT_CONTROL);
|
|
|
|
ad_write(sc, SP_RIGHT_OUTPUT_CONTROL, OUTPUT_MUTE|reg);
|
|
|
|
} else if (!sc->mon_mute) {
|
|
|
|
DPRINTF(("cs4231_mute_monitor: unmuting\n"));
|
|
|
|
reg = ad_read(sc, SP_LEFT_OUTPUT_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_OUTPUT_CONTROL, reg & ~OUTPUT_MUTE);
|
|
|
|
reg = ad_read(sc, SP_RIGHT_OUTPUT_CONTROL);
|
|
|
|
ad_write(sc, SP_RIGHT_OUTPUT_CONTROL, reg & ~OUTPUT_MUTE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
cs4231_mute_mono(sc, mute)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int mute;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
if (mute) {
|
|
|
|
DPRINTF(("cs4231_mute_mono: muting\n"));
|
|
|
|
reg = ad_read(sc, CS_MONO_IO_CONTROL);
|
|
|
|
ad_write(sc, CS_MONO_IO_CONTROL, MONO_INPUT_MUTE|reg);
|
|
|
|
} else if (!sc->mono_mute) {
|
|
|
|
DPRINTF(("cs4231_mute_mono: unmuting\n"));
|
|
|
|
reg = ad_read(sc, CS_MONO_IO_CONTROL);
|
|
|
|
ad_write(sc, CS_MONO_IO_CONTROL, reg & ~MONO_INPUT_MUTE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
cs4231_mute_line(sc, mute)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int mute;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
if (mute) {
|
|
|
|
DPRINTF(("cs4231_mute_line: muting\n"));
|
|
|
|
reg = ad_read(sc, CS_LEFT_LINE_CONTROL);
|
|
|
|
ad_write(sc, CS_LEFT_LINE_CONTROL, LINE_INPUT_MUTE|reg);
|
|
|
|
reg = ad_read(sc, CS_RIGHT_LINE_CONTROL);
|
|
|
|
ad_write(sc, CS_RIGHT_LINE_CONTROL, LINE_INPUT_MUTE|reg);
|
|
|
|
} else if (!sc->line_mute) {
|
|
|
|
DPRINTF(("cs4231_mute_line: unmuting\n"));
|
|
|
|
reg = ad_read(sc, CS_LEFT_LINE_CONTROL);
|
|
|
|
ad_write(sc, CS_LEFT_LINE_CONTROL, reg & ~LINE_INPUT_MUTE);
|
|
|
|
reg = ad_read(sc, CS_RIGHT_LINE_CONTROL);
|
|
|
|
ad_write(sc, CS_RIGHT_LINE_CONTROL, reg & ~LINE_INPUT_MUTE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ad1848_mute_aux1(sc, mute)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int mute;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
if (mute) {
|
|
|
|
DPRINTF(("ad1848_mute_aux1: muting\n"));
|
|
|
|
reg = ad_read(sc, SP_LEFT_AUX1_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_AUX1_CONTROL, AUX_INPUT_MUTE|reg);
|
|
|
|
reg = ad_read(sc, SP_RIGHT_AUX1_CONTROL);
|
|
|
|
ad_write(sc, SP_RIGHT_AUX1_CONTROL, AUX_INPUT_MUTE|reg);
|
|
|
|
} else if (!sc->aux1_mute) {
|
|
|
|
DPRINTF(("ad1848_mute_aux1: unmuting\n"));
|
|
|
|
reg = ad_read(sc, SP_LEFT_AUX1_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_AUX1_CONTROL, reg & ~AUX_INPUT_MUTE);
|
|
|
|
reg = ad_read(sc, SP_RIGHT_AUX1_CONTROL);
|
|
|
|
ad_write(sc, SP_RIGHT_AUX1_CONTROL, reg & ~AUX_INPUT_MUTE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ad1848_mute_aux2(sc, mute)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int mute;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
if (mute) {
|
|
|
|
DPRINTF(("ad1848_mute_aux2: muting\n"));
|
|
|
|
reg = ad_read(sc, SP_LEFT_AUX2_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_AUX2_CONTROL, AUX_INPUT_MUTE|reg);
|
|
|
|
reg = ad_read(sc, SP_RIGHT_AUX2_CONTROL);
|
|
|
|
ad_write(sc, SP_RIGHT_AUX2_CONTROL, AUX_INPUT_MUTE|reg);
|
|
|
|
} else if (!sc->aux2_mute) {
|
|
|
|
DPRINTF(("ad1848_mute_aux2: unmuting\n"));
|
|
|
|
reg = ad_read(sc, SP_LEFT_AUX2_CONTROL);
|
|
|
|
ad_write(sc, SP_LEFT_AUX2_CONTROL, reg & ~AUX_INPUT_MUTE);
|
|
|
|
reg = ad_read(sc, SP_RIGHT_AUX2_CONTROL);
|
|
|
|
ad_write(sc, SP_RIGHT_AUX2_CONTROL, reg & ~AUX_INPUT_MUTE);
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_aux1_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
u_int atten;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_aux1_gain: %d:%d\n", gp->left, gp->right));
|
|
|
|
|
|
|
|
sc->aux1_gain = *gp;
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->left) * AUX_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_LEFT_AUX1_CONTROL);
|
|
|
|
reg &= ~(AUX_INPUT_ATTEN_BITS);
|
|
|
|
ad_write(sc, SP_LEFT_AUX1_CONTROL, (atten&0x1f)|reg);
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->right) * AUX_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_RIGHT_AUX1_CONTROL);
|
|
|
|
reg &= ~(AUX_INPUT_ATTEN_BITS);
|
|
|
|
ad_write(sc, SP_RIGHT_AUX1_CONTROL, (atten&0x1f)|reg);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_aux1_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->aux1_gain;
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
int
|
|
|
|
cs4231_set_linein_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
u_char reg, oregl, oregr;
|
|
|
|
u_int atten;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_linein_gain: %d:%d\n", gp->left, gp->right));
|
|
|
|
|
|
|
|
sc->line_gain = *gp;
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->left) * LINE_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
oregl = reg = ad_read(sc, CS_LEFT_LINE_CONTROL);
|
|
|
|
reg &= ~(LINE_INPUT_ATTEN_BITS);
|
|
|
|
ad_write(sc, CS_LEFT_LINE_CONTROL, (atten&LINE_INPUT_ATTEN_BITS)|reg);
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->right) * LINE_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
oregr = reg = ad_read(sc, CS_RIGHT_LINE_CONTROL);
|
|
|
|
reg &= ~(LINE_INPUT_ATTEN_BITS);
|
|
|
|
ad_write(sc, CS_RIGHT_LINE_CONTROL, (atten&LINE_INPUT_ATTEN_BITS)|reg);
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_linein_gain: was %x:%x\n", oregl, oregr));
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
cs4231_get_linein_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->line_gain;
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
1995-02-21 05:26:39 +03:00
|
|
|
int
|
|
|
|
ad1848_set_aux2_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
u_char reg;
|
|
|
|
u_int atten;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_aux2_gain: %d:%d\n", gp->left, gp->right));
|
|
|
|
|
|
|
|
sc->aux2_gain = *gp;
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->left) * AUX_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_LEFT_AUX2_CONTROL);
|
|
|
|
reg &= ~(AUX_INPUT_ATTEN_BITS);
|
|
|
|
ad_write(sc, SP_LEFT_AUX2_CONTROL, (atten&0x1f)|reg);
|
|
|
|
|
|
|
|
atten = ((AUDIO_MAX_GAIN - gp->right) * AUX_INPUT_ATTEN_BITS)/AUDIO_MAX_GAIN;
|
|
|
|
reg = ad_read(sc, SP_RIGHT_AUX2_CONTROL);
|
|
|
|
reg &= ~(AUX_INPUT_ATTEN_BITS);
|
|
|
|
ad_write(sc, SP_RIGHT_AUX2_CONTROL, (atten&0x1f)|reg);
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_aux2_gain(sc, gp)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
struct ad1848_volume *gp;
|
|
|
|
{
|
|
|
|
*gp = sc->aux2_gain;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_in_sr(addr, sr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_long sr;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_in_sr: %d\n", sr));
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
sc->sc_irate = sc->sc_orate = ad1848_set_speed(sc, sr);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
u_long
|
|
|
|
ad1848_get_in_sr(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(sc->sc_irate);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_out_sr(addr, sr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_long sr;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_out_sr: %d\n", sr));
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
sc->sc_irate = sc->sc_orate = ad1848_set_speed(sc, sr);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
u_long
|
|
|
|
ad1848_get_out_sr(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(sc->sc_orate);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_query_encoding(addr, fp)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
struct audio_encoding *fp;
|
|
|
|
{
|
|
|
|
switch (fp->index) {
|
|
|
|
case 0:
|
1995-07-07 06:11:45 +04:00
|
|
|
strcpy(fp->name, AudioEmulaw);
|
1995-02-21 05:26:39 +03:00
|
|
|
fp->format_id = AUDIO_ENCODING_ULAW;
|
|
|
|
break;
|
|
|
|
case 1:
|
1995-07-07 06:11:45 +04:00
|
|
|
strcpy(fp->name, AudioEalaw);
|
1995-02-21 05:26:39 +03:00
|
|
|
fp->format_id = AUDIO_ENCODING_ALAW;
|
|
|
|
break;
|
|
|
|
case 2:
|
1995-07-07 06:11:45 +04:00
|
|
|
strcpy(fp->name, AudioEpcm16);
|
1995-02-21 05:26:39 +03:00
|
|
|
fp->format_id = AUDIO_ENCODING_PCM16;
|
|
|
|
break;
|
|
|
|
case 3:
|
1995-07-07 06:11:45 +04:00
|
|
|
strcpy(fp->name, AudioEpcm8);
|
1995-02-21 05:26:39 +03:00
|
|
|
fp->format_id = AUDIO_ENCODING_PCM8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return(EINVAL);
|
|
|
|
/*NOTREACHED*/
|
|
|
|
}
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_encoding(addr, enc)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_int enc;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_encoding: %d\n", enc));
|
|
|
|
|
|
|
|
if (sc->encoding != AUDIO_ENCODING_PCM8 &&
|
|
|
|
sc->encoding != AUDIO_ENCODING_PCM16 &&
|
|
|
|
sc->encoding != AUDIO_ENCODING_ALAW &&
|
|
|
|
sc->encoding != AUDIO_ENCODING_ULAW) {
|
|
|
|
|
|
|
|
sc->encoding = AUDIO_ENCODING_PCM8;
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->encoding = ad1848_set_format(sc, enc, sc->precision);
|
|
|
|
|
|
|
|
if (sc->encoding == -1) {
|
|
|
|
sc->encoding = AUDIO_ENCODING_PCM8;
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_encoding(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(sc->encoding);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_precision(addr, prec)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_int prec;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_precision: %d\n", prec));
|
|
|
|
|
|
|
|
sc->encoding = ad1848_set_format(sc, sc->encoding, prec);
|
|
|
|
if (sc->encoding == -1) {
|
|
|
|
sc->encoding = AUDIO_ENCODING_PCM16;
|
|
|
|
sc->precision = 16;
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
sc->precision = prec;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_precision(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(sc->precision);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_channels(addr, chans)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
int chans;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_channels: %d\n", chans));
|
|
|
|
|
|
|
|
if (chans < 1 || chans > 2)
|
|
|
|
return(EINVAL);
|
|
|
|
|
|
|
|
sc->channels = chans;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_channels(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
return(sc->channels);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_rec_port(sc, port)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int port;
|
|
|
|
{
|
|
|
|
u_char inp, reg;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_rec_port: 0x%x\n", port));
|
|
|
|
|
|
|
|
if (port == MIC_IN_PORT) {
|
|
|
|
inp = MIC_INPUT;
|
|
|
|
}
|
|
|
|
else if (port == LINE_IN_PORT) {
|
|
|
|
inp = LINE_INPUT;
|
|
|
|
}
|
|
|
|
else if (port == DAC_IN_PORT) {
|
|
|
|
inp = MIXED_DAC_INPUT;
|
|
|
|
}
|
1995-07-07 06:11:45 +04:00
|
|
|
else if (sc->mode == 2 && port == AUX1_IN_PORT) {
|
|
|
|
inp = AUX_INPUT;
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
else
|
|
|
|
return(EINVAL);
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);
|
|
|
|
reg &= INPUT_SOURCE_MASK;
|
|
|
|
ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp|reg));
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);
|
|
|
|
reg &= INPUT_SOURCE_MASK;
|
|
|
|
ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp|reg));
|
|
|
|
|
|
|
|
sc->rec_port = port;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_get_rec_port(sc)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
{
|
|
|
|
return(sc->rec_port);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_round_blocksize(addr, blk)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
int blk;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
sc->sc_lastcc = -1;
|
|
|
|
|
|
|
|
/* Higher speeds need bigger blocks to avoid popping and silence gaps. */
|
1996-02-06 00:32:26 +03:00
|
|
|
if ((sc->sc_orate > 8000 || sc->sc_irate > 8000) && blk < NBPG/2)
|
1995-02-21 05:26:39 +03:00
|
|
|
blk = NBPG/2;
|
|
|
|
/* don't try to DMA too much at once, though. */
|
|
|
|
if (blk > NBPG)
|
|
|
|
blk = NBPG;
|
|
|
|
|
|
|
|
if (sc->channels == 2)
|
|
|
|
return (blk & ~1); /* must be even to preserve stereo separation */
|
|
|
|
else
|
|
|
|
return(blk); /* Anything goes :-) */
|
|
|
|
}
|
|
|
|
|
|
|
|
u_int
|
|
|
|
ad1848_get_silence(enc)
|
|
|
|
int enc;
|
|
|
|
{
|
|
|
|
#define ULAW_SILENCE 0x7f
|
|
|
|
#define ALAW_SILENCE 0x55
|
|
|
|
#define LINEAR_SILENCE 0
|
|
|
|
u_int auzero;
|
|
|
|
|
|
|
|
switch (enc) {
|
|
|
|
case AUDIO_ENCODING_ULAW:
|
|
|
|
auzero = ULAW_SILENCE;
|
|
|
|
break;
|
|
|
|
case AUDIO_ENCODING_ALAW:
|
|
|
|
auzero = ALAW_SILENCE;
|
|
|
|
break;
|
|
|
|
case AUDIO_ENCODING_PCM8:
|
|
|
|
case AUDIO_ENCODING_PCM16:
|
|
|
|
default:
|
|
|
|
auzero = LINEAR_SILENCE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return(auzero);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_open(sc, dev, flags)
|
|
|
|
struct ad1848_softc *sc;
|
|
|
|
dev_t dev;
|
|
|
|
int flags;
|
|
|
|
{
|
|
|
|
DPRINTF(("ad1848_open: sc=0x%x\n", sc));
|
|
|
|
|
|
|
|
sc->sc_intr = 0;
|
|
|
|
sc->sc_lastcc = -1;
|
|
|
|
sc->sc_locked = 0;
|
|
|
|
|
|
|
|
/* Enable interrupts */
|
|
|
|
DPRINTF(("ad1848_open: enable intrs\n"));
|
|
|
|
ad_write(sc, SP_PIN_CONTROL, INTERRUPT_ENABLE|ad_read(sc, SP_PIN_CONTROL));
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
#ifdef AUDIO_DEBUG
|
1995-02-21 05:26:39 +03:00
|
|
|
if (ad1848debug)
|
|
|
|
ad1848_dump_regs(sc);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
/*
|
|
|
|
* Close function is called at splaudio().
|
|
|
|
*/
|
1995-02-21 05:26:39 +03:00
|
|
|
void
|
|
|
|
ad1848_close(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
register u_char r;
|
|
|
|
|
|
|
|
sc->sc_intr = 0;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_close: stop DMA\n"));
|
|
|
|
ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)0);
|
|
|
|
ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)0);
|
|
|
|
|
|
|
|
/* Disable interrupts */
|
|
|
|
DPRINTF(("ad1848_close: disable intrs\n"));
|
|
|
|
ad_write(sc, SP_PIN_CONTROL, ad_read(sc, SP_PIN_CONTROL) & ~(INTERRUPT_ENABLE));
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_close: disable capture and playback\n"));
|
|
|
|
r = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
r &= ~(CAPTURE_ENABLE|PLAYBACK_ENABLE);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, r);
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
#ifdef AUDIO_DEBUG
|
1995-02-21 05:26:39 +03:00
|
|
|
if (ad1848debug)
|
|
|
|
ad1848_dump_regs(sc);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Lower-level routines
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
ad1848_commit_settings(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
int timeout;
|
|
|
|
u_char fs;
|
|
|
|
int s = splaudio();
|
|
|
|
|
1995-03-25 03:00:53 +03:00
|
|
|
ad1848_mute_monitor(sc, 1);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
ad_set_MCE(sc, 1); /* Enables changes to the format select reg */
|
|
|
|
|
|
|
|
fs = sc->speed_bits | (sc->format_bits << 5);
|
|
|
|
|
|
|
|
if (sc->channels == 2)
|
|
|
|
fs |= FMT_STEREO;
|
|
|
|
|
|
|
|
ad_write(sc, SP_CLOCK_DATA_FORMAT, fs);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If mode == 2 (CS4231), set I28 also. It's the capture format register.
|
|
|
|
*/
|
1995-07-07 06:11:45 +04:00
|
|
|
if (sc->mode == 2) {
|
|
|
|
/* Gravis Ultrasound MAX SDK sources says something about errata
|
|
|
|
* sheets, with the implication that these inb()s are necessary.
|
|
|
|
*/
|
|
|
|
(void) inb(sc->sc_iobase+AD1848_IDATA);
|
|
|
|
(void) inb(sc->sc_iobase+AD1848_IDATA);
|
|
|
|
/*
|
|
|
|
* Write to I8 starts resyncronization. Wait until it completes.
|
|
|
|
*/
|
|
|
|
timeout = 100000;
|
|
|
|
while (timeout > 0 && inb(sc->sc_iobase+AD1848_IADDR) == SP_IN_INIT)
|
|
|
|
timeout--;
|
1995-02-21 05:26:39 +03:00
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
ad_write(sc, CS_REC_FORMAT, fs);
|
|
|
|
/* Gravis Ultrasound MAX SDK sources says something about errata
|
|
|
|
* sheets, with the implication that these inb()s are necessary.
|
|
|
|
*/
|
|
|
|
(void) inb(sc->sc_iobase+AD1848_IDATA);
|
|
|
|
(void) inb(sc->sc_iobase+AD1848_IDATA);
|
|
|
|
/* Now wait for resync for capture side of the house */
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
/*
|
|
|
|
* Write to I8 starts resyncronization. Wait until it completes.
|
|
|
|
*/
|
|
|
|
timeout = 100000;
|
|
|
|
while (timeout > 0 && inb(sc->sc_iobase+AD1848_IADDR) == SP_IN_INIT)
|
|
|
|
timeout--;
|
|
|
|
|
|
|
|
if (inb(sc->sc_iobase+AD1848_IADDR) == SP_IN_INIT)
|
1996-10-13 05:37:04 +04:00
|
|
|
printf("ad1848_commit: Auto calibration timed out\n");
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Starts the calibration process and
|
|
|
|
* enters playback mode after it.
|
|
|
|
*/
|
|
|
|
ad_set_MCE(sc, 0);
|
|
|
|
wait_for_calibration(sc);
|
|
|
|
|
1995-03-25 03:00:53 +03:00
|
|
|
ad1848_mute_monitor(sc, 0);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
sc->sc_lastcc = -1;
|
|
|
|
|
|
|
|
splx(s);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ad1848_reset(sc)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
{
|
1996-04-30 00:02:32 +04:00
|
|
|
#if 0
|
1995-02-21 05:26:39 +03:00
|
|
|
u_char r;
|
1996-04-30 00:02:32 +04:00
|
|
|
#endif
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_reset\n"));
|
|
|
|
|
|
|
|
/* Clear the PEN and CEN bits */
|
|
|
|
#if 0
|
|
|
|
r = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
r &= ~(CAPTURE_ENABLE|PLAYBACK_ENABLE);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, r);
|
|
|
|
#else
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, 0);
|
|
|
|
#endif
|
1995-07-07 06:11:45 +04:00
|
|
|
if (sc->mode == 2) {
|
|
|
|
outb(sc->sc_iobase+AD1848_IADDR, CS_IRQ_STATUS);
|
|
|
|
outb(sc->sc_iobase+AD1848_IDATA, 0);
|
|
|
|
}
|
1995-02-21 05:26:39 +03:00
|
|
|
/* Clear interrupt status */
|
|
|
|
outb(sc->sc_iobase+AD1848_STATUS, 0);
|
1995-07-07 06:11:45 +04:00
|
|
|
#ifdef AUDIO_DEBUG
|
|
|
|
if (ad1848debug)
|
|
|
|
ad1848_dump_regs(sc);
|
|
|
|
#endif
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_speed(sc, arg)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int arg;
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The sampling speed is encoded in the least significant nible of I8. The
|
|
|
|
* LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
|
|
|
|
* three bits select the divisor (indirectly):
|
|
|
|
*
|
|
|
|
* The available speeds are in the following table. Keep the speeds in
|
|
|
|
* the increasing order.
|
|
|
|
*/
|
|
|
|
typedef struct {
|
|
|
|
int speed;
|
|
|
|
u_char bits;
|
|
|
|
} speed_struct;
|
|
|
|
|
|
|
|
static speed_struct speed_table[] = {
|
|
|
|
{5510, (0 << 1) | 1},
|
|
|
|
{5510, (0 << 1) | 1},
|
|
|
|
{6620, (7 << 1) | 1},
|
|
|
|
{8000, (0 << 1) | 0},
|
|
|
|
{9600, (7 << 1) | 0},
|
|
|
|
{11025, (1 << 1) | 1},
|
|
|
|
{16000, (1 << 1) | 0},
|
|
|
|
{18900, (2 << 1) | 1},
|
|
|
|
{22050, (3 << 1) | 1},
|
|
|
|
{27420, (2 << 1) | 0},
|
|
|
|
{32000, (3 << 1) | 0},
|
|
|
|
{33075, (6 << 1) | 1},
|
|
|
|
{37800, (4 << 1) | 1},
|
|
|
|
{44100, (5 << 1) | 1},
|
|
|
|
{48000, (6 << 1) | 0}
|
|
|
|
};
|
|
|
|
|
|
|
|
int i, n, selected = -1;
|
|
|
|
|
|
|
|
n = sizeof(speed_table) / sizeof(speed_struct);
|
|
|
|
|
|
|
|
if (arg < speed_table[0].speed)
|
|
|
|
selected = 0;
|
|
|
|
if (arg > speed_table[n - 1].speed)
|
|
|
|
selected = n - 1;
|
|
|
|
|
|
|
|
for (i = 1 /*really*/ ; selected == -1 && i < n; i++)
|
|
|
|
if (speed_table[i].speed == arg)
|
|
|
|
selected = i;
|
|
|
|
else if (speed_table[i].speed > arg) {
|
|
|
|
int diff1, diff2;
|
|
|
|
|
|
|
|
diff1 = arg - speed_table[i - 1].speed;
|
|
|
|
diff2 = speed_table[i].speed - arg;
|
|
|
|
|
|
|
|
if (diff1 < diff2)
|
|
|
|
selected = i - 1;
|
|
|
|
else
|
|
|
|
selected = i;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (selected == -1) {
|
1996-10-13 05:37:04 +04:00
|
|
|
printf("ad1848: Can't find speed???\n");
|
1995-02-21 05:26:39 +03:00
|
|
|
selected = 3;
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->speed = speed_table[selected].speed;
|
|
|
|
sc->speed_bits = speed_table[selected].bits;
|
|
|
|
|
|
|
|
return sc->speed;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_set_format(sc, fmt, prec)
|
|
|
|
register struct ad1848_softc *sc;
|
|
|
|
int fmt, prec;
|
|
|
|
{
|
|
|
|
static u_char format2bits[] = {
|
1995-07-07 06:11:45 +04:00
|
|
|
/* AUDIO_ENCODING_ULAW */ FMT_ULAW >> 5,
|
|
|
|
/* AUDIO_ENCODING_ALAW */ FMT_ALAW >> 5,
|
|
|
|
/* AUDIO_ENCODING_PCM16 */ FMT_TWOS_COMP >> 5,
|
|
|
|
/* AUDIO_ENCODING_PCM8 */ FMT_PCM8 >> 5
|
1995-02-21 05:26:39 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_format: fmt=%d prec=%d\n", fmt, prec));
|
|
|
|
|
|
|
|
/* If not linear; force prec to 8bits */
|
|
|
|
if (fmt != AUDIO_ENCODING_PCM16 && prec == 16)
|
|
|
|
prec = 8;
|
|
|
|
|
|
|
|
if (fmt < AUDIO_ENCODING_ULAW || fmt > AUDIO_ENCODING_PCM8)
|
|
|
|
goto nogood;
|
|
|
|
|
|
|
|
if (prec != 8 && prec != 16)
|
|
|
|
goto nogood;
|
|
|
|
|
|
|
|
sc->format_bits = format2bits[fmt-1];
|
|
|
|
|
|
|
|
if (fmt == AUDIO_ENCODING_PCM16 && prec == 8)
|
1995-07-07 06:11:45 +04:00
|
|
|
sc->format_bits = FMT_PCM8 >> 5; /* signed vs. unsigned samples? */
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
DPRINTF(("ad1848_set_format: bits=%x\n", sc->format_bits));
|
|
|
|
|
|
|
|
return fmt;
|
|
|
|
|
|
|
|
nogood:
|
|
|
|
sc->format_bits = 0;
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Halt a DMA in progress.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
ad1848_halt_out_dma(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_char reg;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848: ad1848_halt_out_dma\n"));
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE));
|
|
|
|
sc->sc_locked = 0;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_halt_in_dma(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_char reg;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848: ad1848_halt_in_dma\n"));
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE));
|
|
|
|
sc->sc_locked = 0;
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_cont_out_dma(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_char reg;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848: ad1848_cont_out_dma %s\n", sc->sc_locked?"(locked)":""));
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, (reg | PLAYBACK_ENABLE));
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_cont_in_dma(addr)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
u_char reg;
|
|
|
|
|
|
|
|
DPRINTF(("ad1848: ad1848_cont_in_dma %s\n", sc->sc_locked?"(locked)":""));
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, (reg | CAPTURE_ENABLE));
|
|
|
|
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
/*
|
|
|
|
* DMA input/output are called at splaudio().
|
|
|
|
*/
|
1995-02-21 05:26:39 +03:00
|
|
|
int
|
|
|
|
ad1848_dma_input(addr, p, cc, intr, arg)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
void *p;
|
|
|
|
int cc;
|
1996-04-30 00:02:32 +04:00
|
|
|
void (*intr) __P((void *));
|
1995-02-21 05:26:39 +03:00
|
|
|
void *arg;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
register u_char reg;
|
|
|
|
|
|
|
|
if (sc->sc_locked) {
|
|
|
|
DPRINTF(("ad1848_dma_input: locked\n"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
#ifdef AUDIO_DEBUG
|
1995-02-21 05:26:39 +03:00
|
|
|
if (ad1848debug > 1)
|
|
|
|
Dprintf("ad1848_dma_input: cc=%d 0x%x (0x%x)\n", cc, intr, arg);
|
|
|
|
#endif
|
|
|
|
sc->sc_locked = 1;
|
|
|
|
sc->sc_intr = intr;
|
|
|
|
sc->sc_arg = arg;
|
1996-03-01 07:08:13 +03:00
|
|
|
sc->sc_dma_flags = DMAMODE_READ;
|
1995-02-21 05:26:39 +03:00
|
|
|
sc->sc_dma_bp = p;
|
|
|
|
sc->sc_dma_cnt = cc;
|
1996-03-01 07:08:13 +03:00
|
|
|
isa_dmastart(DMAMODE_READ, p, cc, sc->sc_recdrq);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
if (sc->precision == 16)
|
|
|
|
cc >>= 1;
|
|
|
|
|
|
|
|
if (sc->channels == 2)
|
|
|
|
cc >>= 1;
|
|
|
|
cc--;
|
|
|
|
|
|
|
|
if (sc->sc_lastcc != cc || sc->sc_mode != AUMODE_RECORD) {
|
|
|
|
ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)(cc & 0xff));
|
|
|
|
ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)((cc >> 8) & 0xff));
|
1995-07-07 06:11:45 +04:00
|
|
|
|
1995-02-21 05:26:39 +03:00
|
|
|
if (sc->mode == 2) {
|
1995-07-07 06:11:45 +04:00
|
|
|
ad_write(sc, CS_LOWER_REC_CNT, (u_char)(cc & 0xff));
|
|
|
|
ad_write(sc, CS_UPPER_REC_CNT, (u_char)((cc >> 8) & 0xff));
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
reg = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, (CAPTURE_ENABLE|reg));
|
|
|
|
|
|
|
|
sc->sc_lastcc = cc;
|
|
|
|
sc->sc_mode = AUMODE_RECORD;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ad1848_dma_output(addr, p, cc, intr, arg)
|
1995-03-25 03:00:53 +03:00
|
|
|
void *addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
void *p;
|
|
|
|
int cc;
|
1996-04-30 00:02:32 +04:00
|
|
|
void (*intr) __P((void *));
|
1995-02-21 05:26:39 +03:00
|
|
|
void *arg;
|
|
|
|
{
|
1995-03-25 03:00:53 +03:00
|
|
|
register struct ad1848_softc *sc = addr;
|
1995-02-21 05:26:39 +03:00
|
|
|
register u_char reg;
|
|
|
|
|
|
|
|
if (sc->sc_locked) {
|
|
|
|
DPRINTF(("ad1848_dma_output: locked\n"));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
#ifdef AUDIO_DEBUG
|
1995-02-21 05:26:39 +03:00
|
|
|
if (ad1848debug > 1)
|
|
|
|
Dprintf("ad1848_dma_output: cc=%d 0x%x (0x%x)\n", cc, intr, arg);
|
|
|
|
#endif
|
|
|
|
sc->sc_locked = 1;
|
|
|
|
sc->sc_intr = intr;
|
|
|
|
sc->sc_arg = arg;
|
1996-03-01 07:08:13 +03:00
|
|
|
sc->sc_dma_flags = DMAMODE_WRITE;
|
1995-02-21 05:26:39 +03:00
|
|
|
sc->sc_dma_bp = p;
|
|
|
|
sc->sc_dma_cnt = cc;
|
1996-03-01 07:08:13 +03:00
|
|
|
isa_dmastart(DMAMODE_WRITE, p, cc, sc->sc_drq);
|
1995-02-21 05:26:39 +03:00
|
|
|
|
|
|
|
if (sc->precision == 16)
|
|
|
|
cc >>= 1;
|
|
|
|
|
|
|
|
if (sc->channels == 2)
|
|
|
|
cc >>= 1;
|
|
|
|
cc--;
|
|
|
|
|
|
|
|
if (sc->sc_lastcc != cc || sc->sc_mode != AUMODE_PLAY) {
|
1995-07-07 06:11:45 +04:00
|
|
|
ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)(cc & 0xff));
|
|
|
|
ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)((cc >> 8) & 0xff));
|
|
|
|
reg = ad_read(sc, SP_INTERFACE_CONFIG);
|
|
|
|
ad_write(sc, SP_INTERFACE_CONFIG, (PLAYBACK_ENABLE|reg));
|
|
|
|
sc->sc_lastcc = cc;
|
|
|
|
sc->sc_mode = AUMODE_PLAY;
|
1995-02-21 05:26:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
1995-04-17 16:06:30 +04:00
|
|
|
ad1848_intr(arg)
|
|
|
|
void *arg;
|
1995-02-21 05:26:39 +03:00
|
|
|
{
|
1995-04-17 16:06:30 +04:00
|
|
|
register struct ad1848_softc *sc = arg;
|
1995-02-21 05:26:39 +03:00
|
|
|
int retval = 0;
|
|
|
|
u_char status;
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
/* Get intr status */
|
1995-02-21 05:26:39 +03:00
|
|
|
status = inb(sc->sc_iobase+AD1848_STATUS);
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
#ifdef AUDIO_DEBUG
|
1995-02-21 05:26:39 +03:00
|
|
|
if (ad1848debug > 1)
|
|
|
|
Dprintf("ad1848_intr: intr=0x%x status=%x\n", sc->sc_intr, status);
|
|
|
|
#endif
|
|
|
|
sc->sc_locked = 0;
|
|
|
|
sc->sc_interrupts++;
|
|
|
|
|
1995-07-07 06:11:45 +04:00
|
|
|
/* Handle interrupt */
|
1995-02-21 05:26:39 +03:00
|
|
|
if (sc->sc_intr && (status & INTERRUPT_STATUS)) {
|
|
|
|
/* ACK DMA read because it may be in a bounce buffer */
|
|
|
|
/* XXX Do write to mask DMA ? */
|
1996-03-01 07:08:13 +03:00
|
|
|
if (sc->sc_dma_flags & DMAMODE_READ)
|
1995-07-07 06:11:45 +04:00
|
|
|
isa_dmadone(sc->sc_dma_flags, sc->sc_dma_bp, sc->sc_dma_cnt - 1, sc->sc_recdrq);
|
1995-02-21 05:26:39 +03:00
|
|
|
(*sc->sc_intr)(sc->sc_arg);
|
|
|
|
retval = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear interrupt */
|
|
|
|
if (status & INTERRUPT_STATUS)
|
|
|
|
outb(sc->sc_iobase+AD1848_STATUS, 0);
|
|
|
|
|
|
|
|
return(retval);
|
|
|
|
}
|