2004-07-31 21:28:36 +04:00
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/* $NetBSD: i82801lpcreg.h,v 1.2 2004/07/31 17:28:36 mrg Exp $ */
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2004-03-14 11:04:38 +03:00
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Minoura Makoto.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part
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* register definitions.
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*/
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/*
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* Currently only necessory part is defined (specifically TCO timer function).
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*/
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/*
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* PCI configuration registers
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*/
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#define LPCIB_PCI_PMBASE 0x40
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#define LPCIB_PCI_ACPI_CNTL 0x44
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#define LPCIB_PCI_BIOS_CNTL 0x4e
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#define LPCIB_PCI_TCO_CNTL 0x54
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#define LPCIB_PCI_GPIO_BASE 0x58
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#define LPCIB_PCI_GPIO_CNTL 0x5c
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#define LPCIB_PCI_PIRQA_ROUT 0x60
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#define LPCIB_PCI_PIRQB_ROUT 0x61
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#define LPCIB_PCI_PIRQC_ROUT 0x62
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#define LPCIB_PCI_PIRQD_ROUT 0x63
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#define LPCIB_PCI_SIRQ_CNTL 0x64
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#define LPCIB_PCI_PIRQE_ROUT 0x68
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#define LPCIB_PCI_PIRQF_ROUT 0x69
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#define LPCIB_PCI_PIRQG_ROUT 0x6a
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#define LPCIB_PCI_PIRQH_ROUT 0x6b
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#define LPCIB_PCI_D31_ERR_CFG 0x88
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#define LPCIB_PCI_D31_ERR_STS 0x8a
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#define LPCIB_PCI_PCI_DMA_C 0x90
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#define LPCIB_PCI_GEN_PMCON_1 0xa0
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# define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08
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#define LPCIB_PCI_GEN_PMCON_2 0xa2
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#define LPCIB_PCI_GEN_PMCON_3 0xa4
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#define LPCIB_PCI_STPCLK_DEL 0xa8
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#define LPCIB_PCI_GPI_ROUT 0xb8
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#define LPCIB_PCI_TRP_FWD_EN 0xc0
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#define LPCIB_PCI_MON4_TRP_RNG 0xc4
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#define LPCIB_PCI_MON5_TRP_RNG 0xc5
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#define LPCIB_PCI_MON6_TRP_RNG 0xc6
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#define LPCIB_PCI_MON7_TRP_RNG 0xc7
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#define LPCIB_PCI_MON_TRP_MSK oxcc
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#define LPCIB_PCI_GEN_CNTL 0xd0
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#define LPCIB_PCI_GEN_STA 0xd4
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# define LPCIB_PCI_GEN_STA_SAFE_MODE (1<<2)
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# define LPCIB_PCI_GEN_STA_NO_REBOOT (1<<1)
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#define LPCIB_PCI_BACK_CNTL 0xd5
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#define LPCIB_PCI_RTC_CONF 0xd8
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#define LPCIB_PCI_COM_DEC 0xe0
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#define LPCIB_PCI_LPCFDD_DEC 0xe1
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#define LPCIB_PCI_SND_DEC 0xe2
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#define LPCIB_PCI_FWH_DEC_EN1 0xe3
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#define LPCIB_PCI_GEN1_DEC 0xe4
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#define LPCIB_PCI_LPC_EN 0xe6
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#define LPCIB_PCI_FWH_SEL1 0xe8
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#define LPCIB_PCI_GEN2_DEC 0xec
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#define LPCIB_PCI_FWH_SEL2 0xee
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#define LPCIB_PCI_FWH_DEC_EN2 0xf0
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#define LPCIB_PCI_FUNC_DIS 0xf2
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/*
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* Power management I/O registers
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* (offset from PMBASE)
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*/
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#define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */
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#define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */
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#define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */
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#define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */
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#define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */
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#define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */
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#define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */
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# define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */
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#define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */
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#define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */
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#define LPCIB_SMI_EN 0x30
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# define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18)
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# define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17)
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# define LPCIB_SMI_EN_PERIODIC_EN (1 << 14)
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# define LPCIB_SMI_EN_TCO_EN (1 << 13)
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# define LPCIB_SMI_EN_MCSMI_EN (1 << 11)
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# define LPCIB_SMI_EN_BIOS_RLS (1 << 7)
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# define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6)
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# define LPCIB_SMI_EN_APMC_EN (1 << 5)
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# define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4)
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# define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3)
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# define LPCIB_SMI_EN_BIOS_EN (1 << 2)
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# define LPCIB_SMI_EN_EOS (1 << 1)
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# define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0)
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#define LPCIB_SMI_STS 0x34
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#define LPCIB_ALT_GP_SMI_EN 0x38
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#define LPCIB_ALT_GP_SMI_STS 0x3a
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#define LPCIB_MON_SMI 0x40
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#define LPCIB_DEVACT_STS 0x44
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#define LPCIB_DEVTRAP_EN 0x48
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#define LPCIB_BUS_ADDR_TRACK 0x4c
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#define LPCIB_BUS_CYC_TRACK 0x4e
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#define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */
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# define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */
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2004-03-14 11:04:38 +03:00
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/*
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* System management TCO registers
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* (offset from PMBASE)
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*/
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#define LPCIB_TCO_BASE 0x60
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#define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00)
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#define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01)
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# define LPCIB_TCO_TMR_MASK 0x3f
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#define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02)
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#define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03)
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#define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04)
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#define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06)
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#define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08)
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# define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11)
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# define LPCIB_TCO1_CNT_SEND_NOW (1 << 10)
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# define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9)
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# define LPCIB_TCO1_CNT_NMI_NOW (1 << 8)
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#define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a)
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#define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c)
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#define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d)
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#define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e)
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#define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10)
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/*
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* TCO timer tick. ICH datasheets say:
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* - The timer is clocked at approximately 0.6 seconds
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* - 6 bit; values of 0-3 will be ignored and should not be attempted
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*/
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static inline int
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lpcib_tcotimer_tick_to_second(int tick)
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{
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return tick * 6 / 10;
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}
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static inline int
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lpcib_tcotimer_second_to_tick(int tick)
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{
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return tick * 10 / 6;
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}
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#define LPCIB_TCOTIMER_MIN_TICK 4
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#define LPCIB_TCOTIMER_MAX_TICK 0x3f
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