NetBSD/share/man/man9/pci_intr.9

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.\" $NetBSD: pci_intr.9,v 1.12 2003/06/30 12:10:40 wiz Exp $
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.\"
.\" Copyright (c) 2000 The NetBSD Foundation, Inc.
.\" All rights reserved.
.\"
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.\" This code is derived from software contributed to The NetBSD Foundation
.\" by Bill Sommerfeld
.\"
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.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
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.\" Foundation, Inc. and its contributors.
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.\" contributors may be used to endorse or promote products derived
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.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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.\"
.Dd May 19, 2002
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.Dt PCI_INTR 9
.Os
.Sh NAME
.Nm pci_intr ,
.Nm pci_intr_map ,
.Nm pci_intr_string ,
.Nm pci_intr_establish ,
.Nm pci_intr_disestablish
.Nd PCI bus interrupt manipulation functions
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.Sh SYNOPSIS
.In dev/pci/pcivar.h
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.Ft int
.Fn pci_intr_map "struct pci_attach_args *pa" "pci_intr_handle_t *ih"
.Ft const char *
.Fn pci_intr_string "pci_chipset_t *pc" "pci_intr_handle_t ih"
.Ft void *
.Fn pci_intr_establish "pci_chipset_t *pc" "pci_intr_handle_t ih" \
"int ipl" "int (*intrhand)(void *)" "void *intrarg"
.Ft void
.Fn pci_intr_disestablish "pci_chipset_t *pc" "void *ih"
.Sh DESCRIPTION
The
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.Nm
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functions exist to allow device drivers machine-independent access to
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PCI bus interrupts.
The functions described in this page are typically declared in a port's
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.Aq Pa machine/pci_machdep.h
header file; however, drivers should generally include
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.Aq Pa dev/pci/pcivar.h
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to get other PCI-specific declarations as well.
.Pp
Each driver has an
.Fn attach
function which has a bus-specific
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.Ft attach_args
structure.
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Each driver for a PCI device is passed a pointer to an object of type
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.Ft struct pci_attach_args
which contains, among other things, information about the location
of the device in the PCI bus topology sufficient to allow interrupts
from the device to be handled.
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.Pp
If a driver wishes to establish an interrupt handler for the device,
it should pass the
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.Ft struct pci_attach_args *
to the
.Fn pci_intr_map
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function, which returns zero on success, and nonzero on failure.
The function sets the
.Ft pci_intr_handle_t
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pointed at by its second argument to a machine-dependent value which
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identifies a particular interrupt source.
.Pp
If the driver wishes to refer to the interrupt source in an attach or
error message, it should use the value returned by
.Fn pci_intr_string .
.Pp
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Subsequently, when the driver is prepared to receive interrupts, it
should call
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.Fn pci_intr_establish
to actually establish the handler; when the device interrupts,
.Fa intrhand
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will be called with a single argument
.Fa intrarg ,
and will run at the interrupt priority level
.Fa ipl .
.Pp
The return value of
.Fn pci_intr_establish
may be saved and passed to
.Fn pci_intr_disestablish
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to disable the interrupt handler
when the driver is no longer interested in interrupts from the device.
.Ss PORTING
A port's implementation of
.Fn pci_intr_map
may use the following members of
.Ft struct pci_attach_args
to determine how the device's interrupts are routed.
.Bd -literal
pci_chipset_tag_t pa_pc;
pcitag_t pa_tag;
pcitag_t pa_intrtag; /* intr. appears to come from here */
pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */
pci_intr_line_t pa_intrline; /* intr. routing information */
pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */
.Ed
.Pp
PCI-PCI
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bridges swizzle (permute) interrupt wiring.
Depending on implementation details, it may be more convenient to use
either original or the swizzled interrupt parameters.
The original device tag and interrupt pin can be found in
.Ft pa_tag
and
.Ft pa_rawintrpin
respectively, while the swizzled tag and pin can be found in
.Ft pa_intrtag
and
.Ft pa_intrpin .
.Pp
When a device is attached to a primary bus, both pairs of fields
contain the same values.
When a device is found behind one or more pci-pci bridges,
.Ft pa_intrpin
contains the
.Dq swizzled
interrupt pin number, while
.Ft pa_rawintrpin
contains the original interrupt pin;
.Ft pa_tag
contains the PCI tag of the device itself, and
.Ft pa_intrtag
contains the PCI tag of the uppermost bridge device.