134 lines
4.3 KiB
C
134 lines
4.3 KiB
C
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/* $NetBSD: comreg.h,v 1.1 1996/01/31 23:24:29 mark Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)comreg.h 7.2 (Berkeley) 5/9/91
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*/
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/*
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* NS16550 UART registers
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*/
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#define com_data 0 /* data register (R/W) */
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#define com_dlbl 0 /* divisor latch low (W) */
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#define com_dlbh 4 /* divisor latch high (W) */
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#define com_ier 4 /* interrupt enable (W) */
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#define com_iir 8 /* interrupt identification (R) */
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#define com_fifo 8 /* FIFO control (W) */
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#define com_lctl 12 /* line control register (R/W) */
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#define com_cfcr 12 /* line control register (R/W) */
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#define com_mcr 16 /* modem control register (R/W) */
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#define com_lsr 20 /* line status register (R/W) */
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#define com_msr 24 /* modem status register (R/W) */
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#define com_scratch 28 /* scratch register (R/W) */
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#define COM_FREQ 1843200 /* 16-bit baud rate divisor */
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#define COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
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/* interrupt enable register */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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/* interrupt identification register */
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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#define IIR_RXRDY 0x4
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#define IIR_TXRDY 0x2
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#define IIR_NOPEND 0x1
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_TRIGGER_1 0x00
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#define FIFO_TRIGGER_4 0x40
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#define FIFO_TRIGGER_8 0x80
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#define FIFO_TRIGGER_14 0xc0
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/* line control register */
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#define LCR_DLAB 0x80
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#define LCR_SBREAK 0x40
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#define LCR_PZERO 0x30
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#define LCR_PONE 0x20
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#define LCR_PEVEN 0x10
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#define LCR_PODD 0x00
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#define LCR_PENAB 0x08
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#define LCR_STOPB 0x04
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#define LCR_8BITS 0x03
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#define LCR_7BITS 0x02
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#define LCR_6BITS 0x01
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#define LCR_5BITS 0x00
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/* modem control register */
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#define MCR_LOOPBACK 0x10
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#define MCR_IENABLE 0x08
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* line status register */
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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/* modem status register */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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#define COM_NPORTS 32
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/*
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* WARNING: Serial console is assumed to be at COM1 address
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* and CONUNIT must be 0.
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*/
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#define CONADDR (SERIAL0_CONTROLLER_BASE)
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#define CONUNIT (0)
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