104 lines
3.8 KiB
C
104 lines
3.8 KiB
C
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/* $NetBSD: tx39irreg.h,v 1.1 2000/01/13 17:53:36 uch Exp $ */
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/*
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* Copyright (c) 2000, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Toshiba TX3912 IR module
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*/
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#define TX39_IRCTRL1_REG 0x0a0 /* R/W */
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#define TX39_IRCTRL2_REG 0x0a4 /* W */
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#define TX39_IRTXHOLD_REG 0x0a8 /* W */
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/*
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* IR control 1 register
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*/
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#define TX39_IRCTRL1_CARDET 0x01000000
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#define TX39_IRCTRL1_BAUDVAL_SHIFT 16
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#define TX39_IRCTRL1_BAUDVAL_MASK 0xff
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#define TX39_IRCTRL1_BAUDVAL(cr) \
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(((cr) >> TX39_IRCTRL1_BAUDVAL_SHIFT) & \
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TX39_IRCTRL1_BAUDVAL_MASK)
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#define TX39_IRCTRL1_BAUDVAL_SET(cr, val) \
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((cr) | (((val) << TX39_IRCTRL1_BAUDVAL_SHIFT) & \
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(TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT)))
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#define TX39_IRCTRL1_BAUDVAL_CLR(cr) \
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((cr) &= ~(TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT))
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#define TX39_IRCTRL1_TESTIR 0x00000010 /* don't set */
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#define TX39_IRCTRL1_DTINVERT 0x00000008
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#define TX39_IRCTRL1_RXPWR 0x00000004
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#define TX39_IRCTRL1_ENSTATE 0x00000002
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#define TX39_IRCTRL1_ENCOMSM 0x00000001
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/*
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* IR control 2 register
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*/
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/*
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* period = (PER + 1) * (BAUDVAL + 1) * (1/3.6864MHz)
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*/
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#define TX39_IRCTRL2_PER_SHIFT 24
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#define TX39_IRCTRL2_PER_MASK 0xff
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#define TX39_IRCTRL2_PER_SET(cr, val) \
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((cr) | (((val) << TX39_IRCTRL2_PER_SHIFT) & \
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(TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT)))
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#define TX39_IRCTRL2_PER_CLR(cr) \
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((cr) &= ~(TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT))
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/*
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* on time = ONTIME * (BAUDVAL + 1) * (1/3.6864MHz)
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*/
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#define TX39_IRCTRL2_ONTIME_SHIFT 16
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#define TX39_IRCTRL2_ONTIME_MASK 0xff
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#define TX39_IRCTRL2_ONTIME_SET(cr, val) \
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((cr) | (((val) << TX39_IRCTRL2_ONTIME_SHIFT) & \
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(TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT)))
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#define TX39_IRCTRL2_ONTIME_CLR(cr) \
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((cr) &= ~(TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT))
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/*
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* delay time = (DELAYVAL + 1) * 7.8ms
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*/
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#define TX39_IRCTRL2_DELAYVAL_SHIFT 8
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#define TX39_IRCTRL2_DELAYVAL_MASK 0xff
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#define TX39_IRCTRL2_DELAYVAL_SET(cr, val) \
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((cr) | (((val) << TX39_IRCTRL2_DELAYVAL_SHIFT) & \
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(TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT)))
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#define TX39_IRCTRL2_DELAYVAL_CLR(cr) \
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((cr) &= ~(TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT))
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/*
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* wait time = (DELAYVAL + 1) * (WAITVAL + 1) * 7.8ms
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*/
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#define TX39_IRCTRL2_WAITVAL_SHIFT 0
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#define TX39_IRCTRL2_WAITVAL_MASK 0xff
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#define TX39_IRCTRL2_WAITVAL_SET(cr, val) \
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((cr) | (((val) << TX39_IRCTRL2_WAITVAL_SHIFT) & \
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(TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT)))
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#define TX39_IRCTRL2_WAITVAL_CLR(cr) \
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((cr) &= ~(TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT))
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