80 lines
2.8 KiB
C
80 lines
2.8 KiB
C
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/* $NetBSD: vr4181giureg.h,v 1.1 2002/02/09 18:08:44 sato Exp $ */
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/*-
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* Copyright (c) 2002 SATO Kazumi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* VR4181 GIU (General Purpose I/O Unit) Registers.
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*/
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#define VR4181GIU_NO_REG_W 0xffffffff /* no register */
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#define VR4181GIU_MODE0_REG 0x00
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#define VR4181GIU_MODE0_REG_W 0x00
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#define VR4181GIU_MODE1_REG_W 0x02
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#define VR4181GIU_MODE2_REG_W 0x04
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#define VR4181GIU_MODE3_REG_W 0x06
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#define VR4181GIU_MODE_GPIO 0x0
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#define VR4181GIU_MODE_ALT 0x1
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/* VR4181GIU_MODE_GPIO */
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#define VR4181GIU_MODE_IN 0x0
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#define VR4181GIU_MODE_OUT 0x2
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/* VR4181GIU_MODE_ALT */
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#define VR4181GIU_MODE_ALT1 0x0
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#define VR4181GIU_MODE_ALT2 0x2
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#define VR4181GIU_PIOD_REG 0x08
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#define VR4181GIU_PIOD_L_REG_W 0x08
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#define VR4181GIU_PIOD_H_REG_W 0x0a
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#define VR4181GIU_INTEN_REG_W 0x0c
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#define VR4181GIU_INTMASK_REG_W 0x0e
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#define VR4181GIU_INTTYP_REG 0x10
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#define VR4181GIU_INTTYP_L_REG_W 0x10
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#define VR4181GIU_INTTYP_H_REG_W 0x12
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#define VR4181GIU_INTSTAT_REG_W 0x14
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#define VR4181GIU_HIBST_REG 0x16
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#define VR4181GIU_HIBST_L_REG_W 0x16
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#define VR4181GIU_HIBST_H_REG_W 0x18
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#define VR4181GIU_SICTL_REG_W 0x1a
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#define VR4181GIU_KEYEN_REG_W 0x1c
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#define VR4181GIU_INTTYP_EDGE 0
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#define VR4181GIU_INTTYP_LEVEL 0x2
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#define VR4181GIU_INTTYP_HIGH 1
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#define VR4181GIU_INTTYP_LOW 0
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/* END vr4181giu.h */
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