172 lines
5.5 KiB
C
172 lines
5.5 KiB
C
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/* $NetBSD: if_eareg.h,v 1.1 1996/01/31 23:25:40 mark Exp $ */
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/*
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* Copyright (c) 1995 Mark Brinicombe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* if_eareg.h
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*
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* Ether3 device driver
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*
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* Created : 08/07/95
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* Last updated : 10/07/95
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*
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* $Id: if_eareg.h,v 1.1 1996/01/31 23:25:40 mark Exp $
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*/
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/*
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* SEEQ 8005 Register Definitions
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*/
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#define EA_8005_BASE 0x000
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/*
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* SEEQ 8005 registers
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*/
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#define EA_8005_COMMAND 0x000
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#define EA_8005_STATUS 0x000
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#define EA_8005_CONFIG1 0x040
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#define EA_8005_CONFIG2 0x080
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#define EA_8005_RX_END 0x0c0
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#define EA_8005_BUFWIN 0x100
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#define EA_8005_RX_PTR 0x140
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#define EA_8005_TX_PTR 0x180
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#define EA_8005_DMA_ADDR 0x1c0
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/* */
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#define EA_CMD_DMA_INTEN (1 << 0)
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#define EA_CMD_RX_INTEN (1 << 1)
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#define EA_CMD_TX_INTEN (1 << 2)
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#define EA_CMD_BW_INTEN (1 << 3)
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#define EA_CMD_DMA_INTACK (1 << 4)
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#define EA_CMD_RX_INTACK (1 << 5)
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#define EA_CMD_TX_INTACK (1 << 6)
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#define EA_CMD_BW_INTACK (1 << 7)
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#define EA_CMD_DMA_ON (1 << 8)
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#define EA_CMD_RX_ON (1 << 9)
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#define EA_CMD_TX_ON (1 << 10)
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#define EA_CMD_DMA_OFF (1 << 11)
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#define EA_CMD_RX_OFF (1 << 12)
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#define EA_CMD_TX_OFF (1 << 13)
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#define EA_CMD_FIFO_READ (1 << 14)
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#define EA_CMD_FIFO_WRITE (1 << 15)
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#define EA_STATUS_DMA_INT (1 << 4)
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#define EA_STATUS_RX_INT (1 << 5)
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#define EA_STATUS_TX_INT (1 << 6)
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#define EA_STATUS_RX_ON (1 << 9)
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#define EA_STATUS_TX_ON (1 << 10)
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#define EA_STATUS_FIFO_FULL (1 << 13)
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#define EA_STATUS_FIFO_EMPTY (1 << 14)
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#define EA_STATUS_FIFO_DIR (1 << 15)
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#define EA_STATUS_FIFO_READ (1 << 15)
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#define EA_CFG1_DMA_BURST_CONT 0x00
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#define EA_CFG1_DMA_BURST_800 0x10
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#define EA_CFG1_DMA_BURST_1600 0x20
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#define EA_CFG1_DMA_BURST_3200 0x30
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#define EA_CFG1_DMA_BSIZE_1 0x00
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#define EA_CFG1_DMA_BSIZE_4 0x40
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#define EA_CFG1_DMA_BSIZE_8 0x80
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#define EA_CFG1_DMA_BSIZE_16 0xc0
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#define EA_CFG1_STATION_ADDR0 (1 << 8)
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#define EA_CFG1_STATION_ADDR1 (1 << 9)
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#define EA_CFG1_STATION_ADDR2 (1 << 10)
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#define EA_CFG1_STATION_ADDR3 (1 << 11)
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#define EA_CFG1_STATION_ADDR4 (1 << 12)
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#define EA_CFG1_STATION_ADDR5 (1 << 13)
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#define EA_CFG1_SPECIFIC ((0 << 15) | (0 << 14))
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#define EA_CFG1_BROADCAST ((0 << 15) | (1 << 14))
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#define EA_CFG1_MULTICAST ((1 << 15) | (0 << 14))
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#define EA_CFG1_PROMISCUOUS ((1 << 15) | (1 << 14))
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#define EA_CFG2_BYTESWAP (1 << 0)
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#define EA_CFG2_CRC_ERR_ENABLE (1 << 3)
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#define EA_CFG2_DRIB_ERR_ENABLE (1 << 4)
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#define EA_CFG2_PASS_SHORT (1 << 5)
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#define EA_CFG2_SLOT_SELECT (1 << 6)
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#define EA_CFG2_PREAM_SELECT (1 << 7)
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#define EA_CFG2_ADDR_LENGTH (1 << 8)
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#define EA_CFG2_RX_CRC (1 << 9)
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#define EA_CFG2_NO_TX_CRC (1 << 10)
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#define EA_CFG2_LOOPBACK (1 << 11)
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#define EA_CFG2_OUTPUT (1 << 12)
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#define EA_CFG2_RESET (1 << 15)
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#define EA_BUFCODE_STATION_ADDR0 0x00
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#define EA_BUFCODE_STATION_ADDR1 0x01
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#define EA_BUFCODE_STATION_ADDR2 0x02
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#define EA_BUFCODE_STATION_ADDR3 0x03
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#define EA_BUFCODE_STATION_ADDR4 0x04
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#define EA_BUFCODE_STATION_ADDR5 0x05
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#define EA_BUFCODE_ADDRESS_PROM 0x06
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#define EA_BUFCODE_TX_EAP 0x07
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#define EA_BUFCODE_LOCAL_MEM 0x08
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#define EA_BUFCODE_INT_VECTOR 0x09
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/*#define EA_BUFCODE_MULTICAST 0x0f*/
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#define EA_PKTHDR_TX (1 << 7)
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#define EA_PKTHDR_RX (0 << 7)
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#define EA_PKTHDR_CHAIN_CONT (1 << 6)
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#define EA_PKTHDR_DATA_FOLLOWS (1 << 5)
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#define EA_PKTHDR_DONE (1 << 7)
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#define EA_TXHDR_BABBLE (1 << 0)
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#define EA_TXHDR_COLLISION (1 << 1)
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#define EA_TXHDR_COLLISION16 (1 << 2)
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#define EA_TXHDR_BABBLE_INT (1 << 0)
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#define EA_TXHDR_COLLISION_INT (1 << 1)
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#define EA_TXHDR_COLLISION16_INT (1 << 2)
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#define EA_TXHDR_XMIT_SUCCESS_INT (1 << 3)
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#define EA_TXHDR_ERROR_MASK (0x07)
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#define EA_RXHDR_OVERSIZE (1 << 0)
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#define EA_RXHDR_CRC_ERROR (1 << 1)
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#define EA_RXHDR_DRIBBLE_ERROR (1 << 2)
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#define EA_RXHDR_SHORT_FRAME (1 << 3)
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#define EA_BUFFER_SIZE 0x10000
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#define EA_TX_BUFFER_SIZE 0x4000
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#define EA_RX_BUFFER_SIZE 0xC000
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/* Packet buffer size */
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#define EA_BUFSIZ 2048
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/* End of if_eareg.h */
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