2015-03-22 16:53:33 +03:00
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/* $NetBSD: amlogic_vpureg.h,v 1.2 2015/03/22 13:53:33 jmcneill Exp $ */
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2015-03-21 04:17:00 +03:00
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_AMLOGIC_VPUREG_H
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#define _ARM_AMLOGIC_VPUREG_H
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#define VPU_REG(n) ((n) << 2)
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#define VIU_OSD2_CTRL_STAT_REG VPU_REG(0x1a30)
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#define VIU_OSD2_BLK0_CFG_W0_REG VPU_REG(0x1a3b)
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#define VIU_OSD2_BLK0_CFG_W1_REG VPU_REG(0x1a3c)
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#define VIU_OSD2_BLK0_CFG_W2_REG VPU_REG(0x1a3d)
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#define VIU_OSD2_BLK0_CFG_W3_REG VPU_REG(0x1a3e)
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#define VIU_OSD2_BLK0_CFG_W4_REG VPU_REG(0x1a64)
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#define VPP_MISC_REG VPU_REG(0x1d26)
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2015-03-22 16:53:33 +03:00
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#define VPP_OSD_VSC_PHASE_STEP_REG VPU_REG(0x1dc0)
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#define VPP_OSD_VSC_INI_PHASE_REG VPU_REG(0x1dc1)
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#define VPP_OSD_VSC_CTRL0_REG VPU_REG(0x1dc2)
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#define VPP_OSD_HSC_PHASE_STEP_REG VPU_REG(0x1dc3)
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#define VPP_OSD_HSC_INI_PHASE_REG VPU_REG(0x1dc4)
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#define VPP_OSD_HSC_CTRL0_REG VPU_REG(0x1dc5)
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#define VPP_OSD_SC_DUMMY_DATA_REG VPU_REG(0x1dc7)
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#define VPP_OSD_SC_CTRL0_REG VPU_REG(0x1dc8)
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#define VPP_OSD_SCI_WH_M1_REG VPU_REG(0x1dc9)
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#define VPP_OSD_SCO_H_REG VPU_REG(0x1dca)
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#define VPP_OSD_SCO_V_REG VPU_REG(0x1dcb)
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2015-03-21 04:17:00 +03:00
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#define VIU_OSD_CTRL_STAT_ENABLE __BIT(21)
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#define VIU_OSD_CTRL_STAT_BLK3_ENABLE __BIT(3)
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#define VIU_OSD_CTRL_STAT_BLK2_ENABLE __BIT(2)
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#define VIU_OSD_CTRL_STAT_BLK1_ENABLE __BIT(1)
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#define VIU_OSD_CTRL_STAT_BLK0_ENABLE __BIT(0)
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#define VIU_OSD_BLK_CFG_W0_TBL_ADDR __BITS(23,16)
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#define VIU_OSD_BLK_CFG_W0_LITTLE_ENDIAN __BIT(15)
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#define VIU_OSD_BLK_CFG_W0_RPT_Y __BIT(14)
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#define VIU_OSD_BLK_CFG_W0_INTERP_CTRL __BITS(13,12)
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#define VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE __BITS(11,8)
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#define VIU_OSD_BLK_CFG_W0_RGB_EN __BIT(7)
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#define VIU_OSD_BLK_CFG_W0_TC_ALPHA_EN __BIT(6)
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#define VIU_OSD_BLK_CFG_W0_COLOR_MATRIX __BITS(5,2)
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#define VIU_OSD_BLK_CFG_W0_INTERLACE_EN __BIT(1)
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#define VIU_OSD_BLK_CFG_W0_INTERLACE_SEL_ODD __BIT(0)
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#define VIU_OSD_BLK_CFG_W1_X_END __BITS(28,16)
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#define VIU_OSD_BLK_CFG_W1_X_START __BITS(12,0)
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#define VIU_OSD_BLK_CFG_W2_Y_END __BITS(28,16)
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#define VIU_OSD_BLK_CFG_W2_Y_START __BITS(12,0)
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#define VIU_OSD_BLK_CFG_W3_H_END __BITS(27,16)
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#define VIU_OSD_BLK_CFG_W3_H_START __BITS(11,0)
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#define VIU_OSD_BLK_CFG_W4_V_END __BITS(27,16)
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#define VIU_OSD_BLK_CFG_W4_V_START __BITS(11,0)
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#define VPP_MISC_POSTBLEND __BIT(7)
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2015-03-22 16:53:33 +03:00
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#define VPP_OSD_VSC_PHASE_STEP_FORMAT __BITS(27,0)
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#define VPP_OSD_VSC_INI_PHASE_0 __BITS(31,16)
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#define VPP_OSD_VSC_INI_PHASE_1 __BITS(15,0)
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#define VPP_OSD_VSC_CTRL0_VSCALE_EN __BIT(24)
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#define VPP_OSC_VSC_CTRL0_INTERLACE __BIT(23)
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#define VPP_OSD_VSC_CTRL0_BOT_RPT_P0_NUM0 __BITS(17,16)
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#define VPP_OSD_VSC_CTRL0_BOT_INI_RCV_NUM0 __BITS(14,11)
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#define VPP_OSD_VSC_CTRL0_TOP_RPT_P0_NUM0 __BITS(9,8)
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#define VPP_OSD_VSC_CTRL0_TOP_INI_RCV_NUM0 __BITS(6,3)
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#define VPP_OSD_VSC_CTRL0_BANK_LENGTH __BITS(2,0)
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#define VPP_OSD_HSC_PHASE_STEP_FORMAT __BITS(27,0)
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#define VPP_OSD_HSC_INI_PHASE_0 __BITS(31,16)
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#define VPP_OSD_HSC_INI_PHASE_1 __BITS(15,0)
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#define VPP_OSD_HSC_CTRL0_HSCALE_EN __BIT(22)
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#define VPP_OSD_HSC_CTRL0_RPT_P0_NUM0 __BITS(9,8)
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#define VPP_OSD_HSC_CTRL0_INI_RCV_NUM0 __BITS(6,3)
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#define VPP_OSD_HSC_CTRL0_BANK_LENGTH __BITS(2,0)
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#define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD1_ALPHA_MODE __BIT(14)
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#define VPP_OSD_SC_CTRL0_OSC_SC_DIN_OSD2_ALPHA_MODE __BIT(13)
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#define VPP_OSD_SC_CTRL0_OSC_SC_ALPHA_MODE __BIT(12)
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#define VPP_OSD_SC_CTRL0_DEFAULT_ALPHA __BITS(11,4)
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#define VPP_OSD_SC_CTRL0_OSD_SC_PATH_EN __BIT(3)
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#define VPP_OSD_SC_CTRL0_OSD_SC_SEL __BITS(1,0)
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#define VPP_OSD_SCI_WH_M1_WIDTH __BITS(28,16)
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#define VPP_OSD_SCI_WH_M1_HEIGHT __BITS(12,0)
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#define VPP_OSD_SCO_H_START __BITS(28,16)
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#define VPP_OSD_SCO_H_END __BITS(12,0)
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#define VPP_OSD_SCO_V_START __BITS(28,16)
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#define VPP_OSD_SCO_V_END __BITS(12,0)
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2015-03-21 04:17:00 +03:00
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#endif /* _ARM_AMLOGIC_VPUREG_H */
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