2001-02-23 07:31:18 +03:00
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/* $NetBSD: sa11x0_lcdreg.h,v 1.2 2001/02/23 04:31:19 ichiro Exp $ */
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2001-02-23 06:48:06 +03:00
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ichiro FUKUHARA.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* #define SALCD_BASE 0xd0010000 */
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/* size of I/O space */
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#define SALCD_NPORTS 11
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/* LCD framebuffer offset */
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#define SALCD_12_16_OFFSET 0x20 /* 12BIT - 16BIT */
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#define SALCD_8BIT_OFFSET 0x200 /* 8BIT */
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/* LCD Control Register 0 */
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#define SALCD_CR0 0
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#define CR0_LEN (1<<0) /* LCD enable */
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#define CR0_CMS (1<<1) /* color op enable */
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#define CR0_SDS (1<<2) /* Single display or Double display */
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#define CR0_LDM (1<<3) /* LDD status bit ignore(dont intrrupt) */
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#define CR0_BAM (1<<4) /* Base address update does not
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generate an intrrupt */
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#define CR0_ERM (1<<5) /* Bus error generate an intrrupt */
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#define CR0_PAS (1<<7) /* Passive / Active and TFT-LCD enable */
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#define CR0_BLE (1<<8) /* endial select 0=little */
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#define CR0_DPD (1<<9)
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/* LCD Control Register 1 */
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#define SALCD_CR1 8
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/* PPL ; Pixel per line - 16 */
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/* HSW ; */
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/* ELW ; */
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/* BLW ; */
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/* LCD Control Register 2 */
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#define SALCD_CR2 9
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/* LPP ; Lines per panel */
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/* VSW ; */
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/* EFW ; */
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/* BFW ; */
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/* LCD Control Register 3 */
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#define SALCD_CR3 10
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/* PCD ; Pixel clock divisor */
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/* ACB ; */
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/* API ; AC Bias */
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/* VSP ; Vertical sync */
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/* HSP ; Horizontal sync */
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/* PCP ; Pixel clock polarity */
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/* DMA Channel 1 Base Address Register */
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#define SALCD_BA1 4
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/* DMA Channel 1 Current Address Register */
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#define SALCD_CA1 5
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/* DMA Channel 1 Base Address Register */
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#define SALCD_BA2 6
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/* DMA Channel 1 Current Address Register */
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#define SALCD_CA2 7
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/* LCD Status Register */
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#define SALCD_SR 1
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#define SR_LDD (1<<0)
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#define SR_BAU (1<<1)
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#define SR_BER (1<<2)
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#define SR_ABC (1<<3)
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#define SR_IOL (1<<4)
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#define SR_IUL (1<<5)
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#define SR_IOU (1<<6)
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#define SR_IUU (1<<7)
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#define SR_OOL (1<<8)
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#define SR_OUL (1<<9)
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#define SR_OOU (1<<10)
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#define SR_OUU (1<<11)
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/* end of sa11x0_lcdreg.h */
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