452 lines
14 KiB
C
452 lines
14 KiB
C
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/* $NetBSD: esp.c,v 1.1 1998/07/05 07:53:45 dbj Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994 Peter Galbavy
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* Copyright (c) 1995 Paul Kranenburg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Based on aic6360 by Jarle Greipsland
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*
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* Acknowledgements: Many of the algorithms used in this driver are
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* inspired by the work of Julian Elischer (julian@tfs.com) and
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* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
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*/
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/*
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* Grabbed from the sparc port at revision 1.73 for the NeXT.
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* Darrin B. Jewell <dbj@netbsd.org> Sat Jul 4 15:41:32 1998
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <next68k/next68k/isr.h>
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#include <next68k/dev/nextdmareg.h>
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#include <next68k/dev/nextdmavar.h>
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#include "espreg.h"
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#include "espvar.h"
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void espattach_intio __P((struct device *, struct device *, void *));
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int espmatch_intio __P((struct device *, struct cfdata *, void *));
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void espattach __P((struct esp_softc *));
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/* Linkup to the rest of the kernel */
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struct cfattach esp_ca = {
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sizeof(struct esp_softc), espmatch_intio, espattach_intio
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};
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struct scsipi_adapter esp_switch = {
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ncr53c9x_scsi_cmd,
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minphys, /* no max at this level; handled by DMA code */
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NULL,
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NULL,
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};
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struct scsipi_device esp_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
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void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int esp_dma_isintr __P((struct ncr53c9x_softc *));
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void esp_dma_reset __P((struct ncr53c9x_softc *));
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int esp_dma_intr __P((struct ncr53c9x_softc *));
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int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void esp_dma_go __P((struct ncr53c9x_softc *));
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void esp_dma_stop __P((struct ncr53c9x_softc *));
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int esp_dma_isactive __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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int
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espmatch_intio(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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/* should probably probe here */
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/* Should also probably set up data from config */
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/* this code isn't working yet, don't match on it */
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return(0);
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}
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void
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espattach_intio(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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esc->sc_bst = NEXT68K_INTIO_BUS_SPACE;
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if (bus_space_map(esc->sc_bst, NEXT_P_SCSI,
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ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) {
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panic("\n%s: can't map ncr53c90 registers\n",
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sc->sc_dev.dv_xname);
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}
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sc->sc_id = 7;
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sc->sc_freq = 20; /* Mhz */
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/* @@@ Some ESP_DCTL bits probably need setting */
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/* Set up SCSI DMA */
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{
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esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE;
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if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR,
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sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) {
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panic("\n%s: can't map scsi DMA registers\n",
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sc->sc_dev.dv_xname);
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}
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esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA;
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esc->sc_scsi_dma.nd_chaining_flag = 0;
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esc->sc_scsi_dma.nd_shutdown_cb = NULL;
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esc->sc_scsi_dma.nd_continue_cb = NULL;
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esc->sc_scsi_dma.nd_completed_cb = NULL;
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esc->sc_scsi_dma.nd_cb_arg = NULL;
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nextdma_config(&esc->sc_scsi_dma);
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}
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espattach(esc);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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espattach(esc)
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struct esp_softc *esc;
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{
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &esp_glue;
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
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sc->sc_cfg3 = NCRCFG3_CDB;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
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(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
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sc->sc_rev = NCR_VARIANT_ESP100;
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} else {
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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if (NCR_READ_REG(sc, NCR_CFG3) !=
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_rev = NCR_VARIANT_ESP200;
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}
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}
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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/*
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* Alas, we must now modify the value a bit, because it's
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* only valid when can switch on FASTCLK and FASTSCSI bits
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* in config register 3...
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*/
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switch (sc->sc_rev) {
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case NCR_VARIANT_ESP100:
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sc->sc_maxxfer = 64 * 1024;
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sc->sc_minsync = 0; /* No synch on old chip? */
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break;
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case NCR_VARIANT_ESP100A:
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sc->sc_maxxfer = 64 * 1024;
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/* Min clocks/byte is 5 */
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sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
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break;
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case NCR_VARIANT_ESP200:
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sc->sc_maxxfer = 16 * 1024 * 1024;
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/* XXX - do actually set FAST* bits */
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break;
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}
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/* Establish interrupt channel */
|
||
|
|
isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc,
|
||
|
|
NEXT_I_IPL(NEXT_I_SCSI), 0);
|
||
|
|
INTR_ENABLE(NEXT_I_SCSI);
|
||
|
|
|
||
|
|
/* register interrupt stats */
|
||
|
|
evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt);
|
||
|
|
|
||
|
|
/* Do the common parts of attachment. */
|
||
|
|
ncr53c9x_attach(sc, &esp_switch, &esp_dev);
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
/* Turn on target selection using the `dma' method */
|
||
|
|
ncr53c9x_dmaselect = 1;
|
||
|
|
|
||
|
|
bootpath_store(1, NULL);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Glue functions.
|
||
|
|
*/
|
||
|
|
|
||
|
|
u_char
|
||
|
|
esp_read_reg(sc, reg)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
int reg;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
|
||
|
|
return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg));
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
esp_write_reg(sc, reg, val)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
int reg;
|
||
|
|
u_char val;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
|
||
|
|
bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
esp_dma_isintr(sc)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
esp_dma_reset(sc)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
esp_dma_intr(sc)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
esp_dma_setup(sc, addr, len, datain, dmasize)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
caddr_t *addr;
|
||
|
|
size_t *len;
|
||
|
|
int datain;
|
||
|
|
size_t *dmasize;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
esp_dma_go(sc)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
esp_dma_stop(sc)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
esp_dma_isactive(sc)
|
||
|
|
struct ncr53c9x_softc *sc;
|
||
|
|
{
|
||
|
|
struct esp_softc *esc = (struct esp_softc *)sc;
|
||
|
|
panic("Not yet implemented");
|
||
|
|
return(0);
|
||
|
|
}
|