196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
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/* $NetBSD: plx9060reg.h,v 1.1 2000/05/17 17:47:00 thorpej Exp $ */
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/*-
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* Copyright (c) 2000 Zembu Labs, Inc.
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* All rights reserved.
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*
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* Author: Jason R. Thorpe <thorpej@zembu.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Zembu Labs, Inc.
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* 4. Neither the name of Zembu Labs nor the names of its employees may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
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* RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS-
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* CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register description for the PLX 9060-family of PCI bus
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* controllers.
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*
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* In order for this file to be really useful to you, you'll want to
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* have the PLX 9060 datasheet in front of you.
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*/
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#ifndef _DEV_PCI_PLX9060REG_H_
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#define _DEV_PCI_PLX9060REG_H_
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/*
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* PLX 9060 PCI configuration space registers.
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*/
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#define PLX_PCI_RUNTIME_MEMADDR 0x10 /* memory mapped 9060 */
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#define PLX_PCI_RUNTIME_IOADDR 0x14 /* i/o mapped 9060 */
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#define PLX_PCI_LOCAL_ADDR0 0x18 /* PCI address of 9060 local bus */
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/*
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* PLX 9060 Runtime registers, in PCI space.
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*/
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/* Local Address Space 0 Range Register */
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#define PLX_LAS0RR 0x00
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#define LASRR_IO 0x00000001
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#define LASRR_MEM_1M 0x00000002
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#define LASRR_MEM_64BIT 0x00000004
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#define LASRR_MEM_PREFETCH 0x00000008
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#define LASRR_MEM_MASK 0xfffffff0
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#define LASRR_IO_MASK 0xfffffffc
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/* Local Address Space 0 Local Base Address (remap) Register */
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#define PLX_LAS0BA 0x04
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#define LASBA_ENABLE 0x00000001
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#define LASBA_MEM_MASK 0xfffffff0
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#define LASBA_IO_MASK 0xfffffffc
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/* Local Arbitration Register */
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#define PLX_LAR 0x08
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#define LAR_LATTMR 0x000000ff
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#define LAR_PAUSETMR 0x0000ff00
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#define LAR_LATTMR_EN 0x00010000
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#define LAR_BREQ_EN 0x00040000
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#define LAR_DSGIVEUP 0x00200000
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#define LAR_DSLOCK_EN 0x00400000
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#define LAR_PCI21_MODE 0x01000000
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/* Big/Little Endian Register */
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#define PLX_ENDIAN 0x0c
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#define ENDIAN_CRBE 0x00000001
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#define ENDIAN_DMBE 0x00000002
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#define ENDIAN_DSAS0BE 0x00000004
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#define ENDIAN_DSAERBE 0x00000008
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#define ENDIAN_BEBL 0x00000010
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/* Expansion ROM Range Register */
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#define PLX_EROMRR 0x10
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#define EROMRR_MASK 0xffffffc0
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/* Expansion ROM Base Address (remap) Register */
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#define PLX_EROMBA 0x14
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#define EROMBA_BREQ_DC 0x0000000f
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#define EROMBA_BREQ_EN 0x00000010
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#define EROMBA_MASK 0xffffffc0
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/* Local Bus Region Descriptor for PCI to Local Access Register */
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#define PLX_LBRD 0x18
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/* Local Range for Direct Master to PCI */
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#define PLX_DMRR 0x1c
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/* Local Bus Base Address for Direct Master to PCI Memory */
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#define PLX_DMLBAM 0x20
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/* Local Bus Base Address for Direct Master to PCI IO/Config */
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#define PLX_DMLBAI 0x24
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/* PCI Base Address (remap) for Direct Master to PCI Memory */
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#define PLX_DMBPAM 0x28
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/* PCI Base Address (remap) for Direct Master to PCI IO/Config */
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#define PLX_DMPBAI 0x2c
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#define PLX_MAILBOX0 0x40 /* Mailbox register 0 */
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#define PLX_MAILBOX1 0x44 /* Mailbox register 1 */
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#define PLX_MAILBOX2 0x48 /* Mailbox register 2 */
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#define PLX_MAILBOX3 0x4c /* Mailbox register 3 */
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#define PLX_MAILBOX4 0x50 /* Mailbox register 4 (not 9060ES) */
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#define PLX_MAILBOX5 0x54 /* Mailbox register 5 (not 9060ES) */
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#define PLX_MAILBOX6 0x58 /* Mailbox register 6 (not 9060ES) */
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#define PLX_MAILBOX7 0x5c /* Mailbox register 7 (not 9060ES) */
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#define PLX_PCI_LOCAL_DOORBELL 0x60 /* PCI -> local doorbell */
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#define PLX_LOCAL_PCI_DOORBELL 0x64 /* local -> PCI doorbell */
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/* Interrupt Control/Status */
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#define PLX_INTCSR 0x68
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#define INTCSR_LSERR_TAMA 0x00000001
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#define INTCSR_LSERR_PA 0x00000002
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#define INTCSR_SERR 0x00000004
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#define INTCSR_PCI_EN 0x00000100
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#define INTCSR_PCIDB_EN 0x00000200
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#define INTCSR_PCIAB_EN 0x00000400
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#define INTCSR_PCILOC_EN 0x00000800
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#define INTCSR_RETRYAB_EN 0x00001000
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#define INTCSR_PCIDB_INT 0x00002000
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#define INTCSR_PCIAB_INT 0x00004000
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#define INTCSR_PCILOC_INT 0x00008000
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#define INTCSR_LOCOE_EN 0x00010000
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#define INTCSR_LOCDB_EN 0x00020000
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#define INTCSR_LOCDB_INT 0x00100000
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#define INTCSR_BIST_INT 0x00800000
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#define INTCSR_DMAB_INT 0x01000000
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#define INTCSR_RETRYAB_INT 0x08000000
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/* EEPROM Control, PCI Command Codes, User I/O Control, Init Control */
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#define PLX_CONTROL 0x6c
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#define CONTROL_PCIMRC 0x00000f00
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#define CONTROL_PCIMRC_SHIFT 8
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#define CONTROL_PCIMWC 0x0000f000
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#define CONTORL_PCIMWC_SHIFT 12
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#define CONTROL_GPO 0x00010000
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#define CONTROL_GPI 0x00020000
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#define CONTROL_EESK 0x01000000
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#define CONTROL_EECS 0x02000000
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#define CONTROL_EEDO 0x04000000 /* PLX -> EEPROM */
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#define CONTROL_EEDI 0x08000000 /* EEPROM -> PLX */
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#define CONTROL_EEPRESENT 0x10000000
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#define CONTROL_RELOADCFG 0x20000000
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#define CONTROL_SWR 0x40000000
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#define CONTROL_LOCALINIT 0x80000000
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/* EEPROM opcodes */
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#define PLX_EEPROM_OPC_READ(x) (0x0080 | ((x) & 0x3f))
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#define PLX_EEPROM_OPC_WRITE(x) (0x0040 | ((x) & 0x3f))
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#define PLX_EEPROM_OPC_WREN 0x0030
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#define PLX_EEPROM_OPC_WRPR 0x0000
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#define PLX_EEPROM_COMMAND(y) (((y) & 0xff) | 0x100)
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/* PCI Configuration ID */
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#define PLX_IDREG 0x70
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#endif /* _DEV_PCI_PLX9060REG_H_ */
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