2019-11-21 06:04:21 +03:00
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/* $NetBSD: ipgphyreg.h,v 1.3 2019/11/21 03:04:21 msaitoh Exp $ */
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2019-10-07 14:53:40 +03:00
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/* $OpenBSD: ipgphyreg.h,v 1.3 2015/07/19 06:28:12 yuo Exp $ */
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/*-
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* Copyright (c) 2006, Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _DEV_MII_IPGPHYREG_H_
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#define _DEV_MII_IPGPHYREG_H_
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/*
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* Registers for the IC Plus IPGA internal PHY.
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*/
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/* PHY specific control & status register. IP1001 only. */
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2019-11-12 17:07:09 +03:00
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#define IPGPHY_SCSR 0x10
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#define IPGPHY_SCSR_RXPHASE_SEL 0x0001
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#define IPGPHY_SCSR_TXPHASE_SEL 0x0002
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#define IPGPHY_SCSR_REPEATOR_MODE 0x0004
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#define IPGPHY_SCSR_RESERVED1_DEF 0x0008
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#define IPGPHY_SCSR_RXCLK_DRV_MASK 0x0060
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#define IPGPHY_SCSR_RXCLK_DRV_DEF 0x0040
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#define IPGPHY_SCSR_RXD_DRV_MASK 0x0180
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#define IPGPHY_SCSR_RXD_DRV_DEF 0x0100
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#define IPGPHY_SCSR_JABBER_ENB 0x0200
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#define IPGPHY_SCSR_HEART_BEAT_ENB 0x0400
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#define IPGPHY_SCSR_DOWNSHIFT_ENB 0x0800
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#define IPGPHY_SCSR_RESERVED2_DEF 0x1000
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#define IPGPHY_SCSR_LED_DRV_4MA 0x0000
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#define IPGPHY_SCSR_LED_DRV_8MA 0x2000
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#define IPGPHY_SCSR_LED_MODE_MASK 0xC000
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#define IPGPHY_SCSR_LED_MODE_DEF 0x0000
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/* PHY link status register. IP1001 only. */
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#define IPGPHY_LSR 0x11
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#define IPGPHY_LSR_JABBER_DET 0x0200
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#define IPGPHY_LSR_APS_SLEEP 0x0400
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#define IPGPHY_LSR_MDIX 0x0800
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#define IPGPHY_LSR_FULL_DUPLEX 0x1000
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#define IPGPHY_LSR_SPEED_10 0x0000
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#define IPGPHY_LSR_SPEED_100 0x2000
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#define IPGPHY_LSR_SPEED_1000 0x4000
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#define IPGPHY_LSR_SPEED_MASK 0x6000
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#define IPGPHY_LSR_LINKUP 0x8000
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/* PHY specific control register 2. IP1001 only. */
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#define IPGPHY_SCR 0x14
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#define IPGPHY_SCR_SEW_RATE_MASK 0x0003
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#define IPGPHY_SCR_SEW_RATE_DEF 0x0003
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#define IPGPHY_SCR_AUTO_XOVER 0x0004
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#define IPGPHY_SCR_SPEED_10_100_ENB 0x0040
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#define IPGPHY_SCR_FIFO_LATENCY_2 0x0000
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#define IPGPHY_SCR_FIFO_LATENCY_3 0x0080
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#define IPGPHY_SCR_FIFO_LATENCY_4 0x0100
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#define IPGPHY_SCR_FIFO_LATENCY_5 0x0180
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#define IPGPHY_SCR_MDIX_ENB 0x0200
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#define IPGPHY_SCR_RESERVED_DEF 0x0400
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#define IPGPHY_SCR_APS_ON 0x0800
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#endif /* _DEV_MII_IPGPHYREG_H_ */
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