129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
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/* $NetBSD: gtintrvar.h,v 1.1 2010/04/28 13:51:56 kiyohara Exp $ */
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/*
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* Copyright (c) 2009 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MARVELL_GTINTRVAR_H_
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#define _MARVELL_GTINTRVAR_H_
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#include <dev/marvell/gtreg.h>
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/*
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* Main Interrupt related functions
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*/
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static __inline uint32_t
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discovery_enable_intr(struct gt_softc *sc, int irq)
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{
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bus_size_t reg;
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uint32_t cim;
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reg = (irq < 32) ? ICR_CIM_LO : ICR_CIM_HI;
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cim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
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cim |= 1 << (irq & 31);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, cim);
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return cim;
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}
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static __inline uint32_t
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discovery_disable_intr(struct gt_softc *sc, int irq)
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{
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bus_size_t reg;
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uint32_t cim;
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reg = (irq < 32) ? ICR_CIM_LO : ICR_CIM_HI;
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cim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
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cim &= ~(1 << (irq & 31));
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, cim);
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return cim;
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}
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static __inline int
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discovery_mic_low(struct gt_softc *sc)
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{
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return bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICR_MIC_LO);
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}
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static __inline int
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discovery_mic_high(struct gt_softc *sc)
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{
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return bus_space_read_4(sc->sc_iot, sc->sc_ioh, ICR_MIC_HI);
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}
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/*
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* GPP Interrupt related functions
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*/
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static __inline uint32_t
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discovery_gpp_enable_intr(struct gt_softc *sc, int pin)
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{
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uint32_t gppim;
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gppim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask);
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gppim |= 1 << pin;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask, gppim);
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return gppim;
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}
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static __inline uint32_t
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discovery_gpp_disable_intr(struct gt_softc *sc, int pin)
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{
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uint32_t gppim;
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gppim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask);
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gppim &= ~(1 << pin);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask, gppim);
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return gppim;
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}
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static __inline void
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discovery_gpp_clear_cause(struct gt_softc *sc, int pin)
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{
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uint32_t gppic;
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gppic =
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause);
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gppic &= ~(1 << pin);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause,
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gppic);
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}
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static __inline int
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discovery_gpp_cause(struct gt_softc *sc)
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{
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return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Cause);
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}
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static __inline int
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discovery_gpp_mask(struct gt_softc *sc)
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{
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return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Interrupt_Mask);
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}
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#endif /* _MARVELL_GTINTRVAR_H_ */
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