145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
/* Copyright 1998 (c) by Salvador Eduardo Tropea
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This code is part of the FreeBE/AF project you can use it under the
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terms and conditions of the FreeBE/AF project. */
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/*
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List of ports used:
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0x3C0,0x3C1,0x3C2,0x3C3,0x3C4,0x3C5,0x3C6,0x3C7,0x3C8,0x3C9,0x3CC,0x3CE,
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0x3CF,0x3D4,0x3D5,0x3DA
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TGUI:
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0x3D8,0x3D9,0x3DB,0x43C6,0x43C7,0x43C8,0x43C9,0x83C6,0x83C8
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0x2100-0x21FF
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*/
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/* CRT (Cathode Rays Tube) Controller Registers
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They control the sync signals.
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0x00 to 0x18 */
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// SVGALib and XFree86 uses <0x18 so they miss the line compare register,
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// don't know why.
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#define CRTbase 0
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#define CRTcant 25
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/* ATT Attribute Controller Registers
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They control some attributes like 16 colors palette, overscan color, etc.
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0x00 to 0x14 */
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#define ATTbase (CRTbase+CRTcant)
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#define ATTcant 21
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/* GRA Graphics Controller Registers
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They control the read/write mode to the video memory.
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0x00 to 0x08 */
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#define GRAbase (ATTbase+ATTcant)
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#define GRAcant 9
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/* SEQ Sequence Registers
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They control how the memory is scanned.
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0x00 to 0x04 */
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#define SEQbase (GRAbase+GRAcant)
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#define SEQcant 5
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/* MOR Miscellaneous Output Register
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1 register */
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#define MORbase (SEQbase+SEQcant)
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#define MORcant 1
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#define VGARegsCant (MORbase+MORcant)
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/* Status values: Here I store special status values that doesn't
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correspond to a physical register but to an operation plus some
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special registers */
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#define SPbase 0
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#define SPcant 12
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#define OldNewStatus SPbase+0
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#define ALT_BNK_WRITE SPbase+1
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#define ALT_BNK_READ SPbase+2
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#define ALT_CLK SPbase+3
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#define DAC_3C6 SPbase+4
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#define DAC_3C6_4th SPbase+5
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#define DAC_WR_ADD SPbase+6
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#define MCLKLOW SPbase+7
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#define MCLKHIG SPbase+8
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#define VCLKLOW SPbase+9
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#define VCLKHIG SPbase+10
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#define DAC_INDEX SPbase+11
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/* ESEQ Extra Sequence Registers
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0x08 to 0x0F (They have some tricks) */
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#define ESEQbase (SPbase+SPcant)
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#define ESEQcant 5
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#define ESEQ_0D_old ESEQbase+0
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#define ESEQ_0E_old ESEQbase+1
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#define ESEQ_0D_new ESEQbase+2
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#define ESEQ_0E_new ESEQbase+3
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#define ESEQ_0F ESEQbase+4
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/* ECRT Extra CRT Registers
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0x19 to 0x50 */
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#define ECRTbase (ESEQbase+ESEQcant)
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#define ECRTcant 33
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#define ECRT_19 ECRTbase
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#define ECRT_1E ECRTbase+1
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#define ECRT_1F ECRTbase+2
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#define ECRT_20 ECRTbase+3
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#define ECRT_21 ECRTbase+4
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#define ECRT_22 ECRTbase+5
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#define ECRT_23 ECRTbase+6
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#define ECRT_24 ECRTbase+7
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#define ECRT_25 ECRTbase+8
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#define ECRT_26 ECRTbase+9
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#define ECRT_27 ECRTbase+10
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#define ECRT_28 ECRTbase+11
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#define ECRT_29 ECRTbase+12
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#define ECRT_2A ECRTbase+13
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#define ECRT_2C ECRTbase+14
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#define ECRT_2F ECRTbase+15
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#define ECRT_30 ECRTbase+16
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#define ECRT_33 ECRTbase+17
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#define ECRT_34 ECRTbase+18
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#define ECRT_35 ECRTbase+19
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#define ECRT_36 ECRTbase+20
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#define ECRT_37 ECRTbase+21
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#define ECRT_38 ECRTbase+22
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#define ECRT_39 ECRTbase+23
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#define ECRT_40 ECRTbase+24
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#define ECRT_41 ECRTbase+25
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#define ECRT_42 ECRTbase+26
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#define ECRT_43 ECRTbase+27
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#define ECRT_44 ECRTbase+28
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#define ECRT_45 ECRTbase+29
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#define ECRT_46 ECRTbase+30
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#define ECRT_47 ECRTbase+31
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#define ECRT_50 ECRTbase+32
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/* EGRA Extra Graphics Controller Registers
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0x0E, 0x0F, 0x23 and 0x2F */
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#define EGRAbase (ECRTbase+ECRTcant)
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#define EGRAcant 4
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#define EGRA_0E_old EGRAbase
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#define EGRA_0F EGRAbase+1
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#define EGRA_23 EGRAbase+2
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#define EGRA_2F EGRAbase+3
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/* EDAC Extra DAC/Clk */
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#define EDACbase (EGRAbase+EGRAcant)
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#define EDACcant 4
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#define EDAC_00 EDACbase+0
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#define EDAC_01 EDACbase+1
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#define EDAC_02 EDACbase+2
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#define EDAC_03 EDACbase+3
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/* GER Graphics Engine Register. Only the relevant stuff */
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/* 0x22 and 0x23 */
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#define GERbase (EDACbase+EDACcant)
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#define GERcant 6
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#define GER_22 GERbase+0
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#define GER_23 GERbase+1
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#define GER_44 GERbase+2
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#define GER_45 GERbase+3
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#define GER_46 GERbase+4
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#define GER_47 GERbase+5
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#define SVGARegsCant (GERbase+GERcant)
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#ifdef __cplusplus
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extern "C" {
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#endif
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int VGASaveRegs(uchar *regs, uchar *Sregs);
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void VGALoadRegs(const uchar *regs,const uchar *Sregs);
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void TGUI9440SaveRegs(uchar *regs);
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void TGUI9440LoadRegs(const uchar *regs);
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#ifdef __cplusplus
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}
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#endif
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