254 lines
8.6 KiB
C
254 lines
8.6 KiB
C
#ifndef CIR_DEFS_H
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#define CIR_DEFS_H
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#include <pc.h>
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typedef enum {
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CLGD5426, // 1
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CLGD5428, // 1
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CLGD5429, // 2
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CLGD5430, // 3
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CLGD5434, // 4
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CLGD5434E, // 5
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CLGD5436, // 6
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CLGD5440, // 7
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CLGD5446, // 8
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CLGD5480, // 9
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CLGD7541, // 10
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CLGD7542, // 11
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CLGD7543, // 10
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CLGD7548, // 12
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CLGD7555, // 13
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CLGD7556 // 13
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} cirrus_types;
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#define KNOWN_CARDS 16
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// 54m30
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// 54m40 - triple buffer, transparent color register
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/*
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1 - the oldest BitBLT capable chips, !!for color-expand with transparency
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transparent color is used !!, maxwidth 2047, maxpitch 4095, maxheight 1023,
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all BitBLT registers except src&dstaddr are preserved, allow at most 7 bits
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to be discarded with color expansion at the end of each scanline, color
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expansion and hw cursor in 8 and 15/16bpp supported
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2 - supports MMIO at b8000 or at the end of linear address space (2mb-256),
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!!for color-expand with transparency 0 bits are just skipped!!, maxpitch 8191,
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color expansion with left edge clipping&pattern vertical preset, supports color
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expanded pattern polygon fills 3 - like 2, ? need srcaddr to be written for
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color expansion system to screen ?, hw cursor also at 24/32bpp 4 - like 3, but
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64 bit, maxwidth 8191, doesn't support clipping&vertical preset and polygon
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fills, color expansion in 32bpp supported, for color expansion with transparency
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all 4 bytes of fg color has to be written and 4 bytes of color has to be filled
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with not fg color, has bug in system to display memory transfers, hw cursor also
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at 24/32bpp, 5 - the bug is corrected 6 - like 2, but 64 bit, maxwidth 8191,
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maxheight 2047,supports solid fill, color expansion in 24 and 32bpp, for 24bpp
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color expansion transparency must be enabled, but can invert the meaning of
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input data, so normal color expansion can de done in two passes, has auto-start
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capability, hw cursor also at 24/32bpp, triple buffer ? 7 - like 3 with video
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features 8 - like 9, no clipping, no X-Y pos. 9 - like 6, has clip rectangle,
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X-Y positioning, command list with possible interrupt on completion, left edge
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clipping more complex, can probably triple buffer, color expand with uses
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transparent color, no transparent mask 10 - (7541,7543) like 1, height is _not_
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preserved 11 - (7542) don't know anything 12 - (7548) like 1 with MMIO,
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autostart, height is _not_ preserved 13 - (7555-6) like 6, MMIO in PCI 0x14 or
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offset 0x3fff00, triple buffer GR16-17, no 32bpp color expansion, autostart if
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banked GR6[3:2]=01,SR17[6]=0,SR17[7:4]=0 else SR17[6]=1,SR17[7:4]!=0
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*/
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typedef struct {
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cirrus_types model;
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int biosnum, pcinum;
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char *desc;
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int family;
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} CIRRUS_DETECT;
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extern unsigned long af_mmio;
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#define GRX 0x3ce
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#define _crtc 0x3d4
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__inline__ void _vsync_out_h( ) {
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do { } while (inportb(0x3DA) & 1); }
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/* _vsync_out_v:
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* Waits until the VGA is not in a vertical retrace.
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*/
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__inline__ void _vsync_out_v( ) {
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do { } while (inportb(0x3DA) & 8); }
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/* _vsync_in:
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* Waits until the VGA is in the vertical retrace period.
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*/
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__inline__ void _vsync_in( ) {
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do { } while (!(inportb(0x3DA) & 8)); }
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/* _write_hpp:
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* Writes to the VGA pelpan register.
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*/
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__inline__ void _write_hpp(int value) {
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write_vga_register(0x3C0, 0x33, value);
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}
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#define outm1(index, value) *(volatile char *)(af_mmio + index) = (value)
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#define outm2(index, value) *(volatile short *)(af_mmio + index) = (value)
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#define outm4(index, value) *(volatile long *)(af_mmio + index) = (value)
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#define inmb(index) *(volatile char *)(af_mmio + index)
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__inline__ void outp1(unsigned short port, unsigned char index,
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unsigned char value) {
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unsigned short w;
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w = index;
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w |= value << 8;
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outportw(port, w);
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}
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__inline__ void outp2(unsigned short port, unsigned char index,
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unsigned short value) {
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unsigned short w;
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w = index;
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w |= ((value & 0xff) << 8);
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outportw(port, w);
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w = index + 1;
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w |= (value & 0xff00);
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outportw(port, w);
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}
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__inline__ void outp3(unsigned short port, unsigned char index,
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unsigned long value) {
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unsigned short w;
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w = index;
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w |= (value & 0xff) << 8;
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outportw(port, w);
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w = index + 1;
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w |= (value & 0xff00);
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outportw(port, w);
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w = index + 2;
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w |= (value >> 8) & 0xff00;
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outportw(port, w);
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}
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#define DISABLE( ) asm volatile("cli");
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#define ENABLE( ) asm volatile("sti");
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#define CIR_FORG8(color) outp1(GRX, 0x01, (color))
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#define CIR_FORG16(color) \
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outp1(GRX, 0x01, (color)&0xff); \
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outp1(GRX, 0x11, ((color) >> 8) & 0xff)
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#define CIR_FORG24(color) \
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outp1(GRX, 0x01, (color)&0xff); \
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outp1(GRX, 0x11, ((color) >> 8) & 0xff); \
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outp1(GRX, 0x13, ((color) >> 16) & 0xff)
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#define CIR_FORG32(color) \
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outp1(GRX, 0x01, (color)&0xff); \
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outp1(GRX, 0x11, ((color) >> 8) & 0xff); \
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outp1(GRX, 0x13, ((color) >> 16) & 0xff); \
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outp1(GRX, 0x15, ((color) >> 24) & 0xff)
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#define CIR_BACKG8(color) outp1(GRX, 0x00, (color))
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#define CIR_BACKG16(color) \
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outp1(GRX, 0x00, (color)&0xff); \
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outp1(GRX, 0x10, ((color) >> 8) & 0xff)
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#define CIR_BACKG24(color) \
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outp1(GRX, 0x00, (color)&0xff); \
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outp1(GRX, 0x10, ((color) >> 8) & 0xff); \
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outp1(GRX, 0x12, ((color) >> 16) & 0xff)
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#define CIR_BACKG32(color) \
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outp1(GRX, 0x00, (color)&0xff); \
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outp1(GRX, 0x10, ((color) >> 8) & 0xff); \
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outp1(GRX, 0x12, ((color) >> 16) & 0xff); \
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outp1(GRX, 0x14, ((color) >> 24) & 0xff)
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#define CIR_FORG8MMIO(color) outm1(0x04, (color))
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#define CIR_FORG16MMIO(color) outm2(0x04, (color))
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#define CIR_FORG24MMIO(color) outm4(0x04, (color))
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#define CIR_FORG32MMIO(color) outm4(0x04, (color))
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#define CIR_BACKG8MMIO(color) outm1(0x00, (color))
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#define CIR_BACKG16MMIO(color) outm2(0x00, (color))
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#define CIR_BACKG24MMIO(color) outm4(0x00, (color))
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#define CIR_BACKG32MMIO(color) outm4(0x00, (color))
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#define SET_WIDTH_HEIGHTMMIO(width, height) \
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outm4(0x08, (width) | (((height) << 16)))
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#define SET_PITCHESMMIO(src, dst) outm4(0x0c,(dst)|((src)<<16)
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#define SET_DSTADDRMMIO(address) outm4(0x10, address)
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/* in last byte of is left edge clipping - to be added */
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#define SET_SRCADDRMMIO(address) outm4(0x14, address)
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#define CIR_ROP_MODEMMIO(rop, mode) outm4(0x18, (mode) | ((rop) << 16))
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#define CIR_BLTROPMMIO(rop) outm1(0x1a, rop)
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#define CIR_BLTMODEMMIO(mode) outm1(0x18, mode)
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#define CIR_WIDTH(width) outp2(GRX, 0x20, width)
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#define CIR_HEIGHT(height) outp2(GRX, 0x22, height)
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#define CIR_DSTPITCH(pitch) outp2(GRX, 0x24, pitch)
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#define CIR_SRCPITCH(pitch) outp2(GRX, 0x26, pitch)
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#define SET_DSTADDR(address) outp3(GRX, 0x28, address)
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#define SET_SRCADDR(address) outp3(GRX, 0x2c, address)
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#define CIR_BLTMODE(mode) outp1(GRX, 0x30, mode)
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#define CIR_BLTROP(rop) outp1(GRX, 0x32, rop)
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#define CIR_TRANS(color) \
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outp2(GRX, 0x34, (color)); \
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outp2(GRX, 0x38, 0);
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#define CIR_TRANSMMIO(color) outm2(0x34, (color))
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#define CIR_CMD(cmd) outp1(GRX, 0x31, cmd)
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#define CIR_CMDMMIO(cmd) outm1(0x40, cmd)
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#define CIR_BLT_PIX8 0
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#define CIR_BLT_PIX15 16
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#define CIR_BLT_PIX16 16
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#define CIR_BLT_PIX24 32
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#define CIR_BLT_PIX32 48
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#define CIR_ROP_COPY 0x0d
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#define CIR_ROP_XOR 0x59
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#define CIR_ROP_AND 0x05
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#define CIR_ROP_OR 0x6d
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#define CIR_ROP_NOP 0x00
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#define CIR_CMD_RUN 0x02
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#define CIR_CMD_BUSY 0x01
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#define CIR_BLT_BACK 0x01
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#define CIR_BLT_TRANS 0x08
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#define CIR_BLT_PATT 0x40
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#define CIR_BLT_MEM 0x04
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#define CIR_BLT_COLEXP 0x80
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#define my_int(num, regs) \
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asm("\
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pushal; \
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pushl %%esi; \
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movl (%%esi),%%edi; \
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movl 8(%%esi),%%ebp; \
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movl 16(%%esi),%%ebx;\
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movl 20(%%esi),%%edx;\
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movl 24(%%esi),%%ecx;\
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movl 28(%%esi),%%eax;\
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pushl 4(%%esi); \
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popl %%esi; \
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int %1; \
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xchgl %%esi,(%%esp); \
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movl %%eax,28(%%esi);\
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movl %%ecx,24(%%esi);\
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movl %%edx,20(%%esi);\
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movl %%ebx,16(%%esi);\
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movl %%ebp,8(%%esi); \
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movl %%edi,(%%esi); \
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popl %%eax; \
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movl %%eax,4(%%esi); \
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popal" ::"S"(regs), \
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"i"(num))
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#endif
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